On Fri, Oct 30, 2009 at 12:55:08PM +0530, Madhavi Manchala wrote: > On Thu, Oct 29, 2009 at 9:11 PM, Sarah Sharp > <sarah.a.sharp@xxxxxxxxxxxxxxx> wrote: > > > The xHCI driver does not support USB selective suspend right now. It's > > probably something I should fix, since most distribution kernels turn it > > on. You'll have to rebuild the 2.6.31.5 kernel with selective suspend > > turned off. > > > > I'm not sure what you're asking. If you have the source for the stable > > tree (at > > git://git.kernel.org/pub/scm/linux/kernel/git/hpa/linux-2.6-allstable.git), > > you can just go into that source tree, type make menuconfig and say 'N' > > to USB selective suspend. Then `make` and `sudo make modules_install > > install` and reboot into the newly compiled kernel. > > Dear Sarah, > > Thanks a lot for your information. > > I did make, make modules_install, make install after turn off the "USB selective > suspend/resume and wakeup" in the make menuconfig. > > However, the xHCI controller recognized the USB 2.0 MS and enumarated > it. When I try to copy some larger data (around 50 MB) from host to > the device, it fails. The behaviour is same on 2.6.32-rc5 kernel also. > Even for small data (2 MB copied mulitple times and copied 8 times one > after the other) also failed. So I can reproduce this, how did you copy the file? Through the command line or through the gnome file manager, or ? > Please find the attached error log file > (large-data-copy-error-xhci.txt), which is taken from dmesg output. Which version of the Fresco Logic host controller are you working with? Is it an FPGA, or does the Fresco chip on the board have a number like 1004? I think your issue is a bug in the xHCI driver, which only hosts that use a particular transfer request buffer (TRB) field would run into. I'll send you a patch shortly. Here's my analysis of your log: [snip] > [ 114.437134] usb-storage: *** thread sleeping. > [ 114.906941] usb-storage: queuecommand called > [ 114.906952] usb-storage: *** thread awakened. > [ 114.906955] usb-storage: Command WRITE_10 (10 bytes) > [ 114.906956] usb-storage: 2a 00 00 0a 81 00 00 00 f0 00 > [ 114.906963] usb-storage: Bulk Command S 0x43425355 T 0x1ed3 L 122880 F 0 Trg 0 LUN 0 CL 10 > [ 114.906965] usb-storage: usb_stor_bulk_transfer_buf: xfer 31 bytes > [ 114.906971] usb 9-2: ep 0x1 - urb len = 0x1f (31), addr = 0x35cdc000, num_trbs = 1 > [ 114.906974] xhci_hcd 0000:03:00.0: Endpoint state = 0x1 > [ 114.906978] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c110 (DMA) > [ 114.906981] xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hf8423004, 32'h2, 4'hf); There's the doorbell write for the setup phase of the MSD command. It's writing to the first slot's doorbell register (offset 0x04) with a value of endpoint index 2, which is correct for endpoint 0x01. > [ 114.906996] xhci_hcd 0000:03:00.0: op reg status = 00000008 > [ 114.906997] xhci_hcd 0000:03:00.0: ir set irq_pending = 00000003 > [ 114.906999] xhci_hcd 0000:03:00.0: Event ring dequeue ptr: > [ 114.907001] xhci_hcd 0000:03:00.0: @3723600 3676c100 00000000 01000000 01028000 This is the last event the driver will see, at 0x3723600 in the event ring. > [ 114.907004] xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hf8420084, 32'h8, 4'hf); > [ 114.907007] xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hf8422020, 32'h3, 4'hf); > [ 114.907010] xhci_hcd 0000:03:00.0: In xhci_handle_event > [ 114.907012] xhci_hcd 0000:03:00.0: xhci_handle_event - OS owns TRB > [ 114.907013] xhci_hcd 0000:03:00.0: xhci_handle_event - calling handle_tx_event > [ 114.907015] xhci_hcd 0000:03:00.0: In handle_tx_event > [ 114.907017] xhci_hcd 0000:03:00.0: handle_tx_event - ep index = 1 > [ 114.907018] xhci_hcd 0000:03:00.0: handle_tx_event - checking for list empty > [ 114.907019] xhci_hcd 0000:03:00.0: handle_tx_event - getting list entry > [ 114.907021] xhci_hcd 0000:03:00.0: handle_tx_event - looking for TD > [ 114.907022] xhci_hcd 0000:03:00.0: handle_tx_event - found event_seg = c3734430 > [ 114.907024] xhci_hcd 0000:03:00.0: Event TRB with TRB type ID 32 > [ 114.907026] xhci_hcd 0000:03:00.0: Offset 0x00 (buffer lo) = 0x3676c100 > [ 114.907027] xhci_hcd 0000:03:00.0: Offset 0x04 (buffer hi) = 0x0 > [ 114.907028] xhci_hcd 0000:03:00.0: Offset 0x08 (transfer length) = 0x1000000 > [ 114.907030] xhci_hcd 0000:03:00.0: Offset 0x0C (flags) = 0x1028000 > [ 114.907032] xhci_hcd 0000:03:00.0: Successful bulk transfer! > [ 114.907033] usb 9-2: ep 0x1 - asked for 31 bytes, 0 bytes untransferred > [ 114.907035] xhci_hcd 0000:03:00.0: Ring deq = 0x3676c110 (DMA) > [ 114.907037] xhci_hcd 0000:03:00.0: Event ring deq = 0x3723610 (DMA) > [ 114.907041] xhci_hcd 0000:03:00.0: // Write event ring dequeue pointer, preserving EHB bit > [ 114.907043] xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 64'hf8422038, 64'h3723610, 4'hf); > [ 114.907045] xhci_hcd 0000:03:00.0: Giveback URB f5ce7a80, len = 31, status = 0 > [ 114.907048] xhci_hcd 0000:03:00.0: xhci_handle_event - returned from handle_tx_event > [ 114.907050] usb-storage: Status code 0; transferred 31/31 > [ 114.907051] usb-storage: -- transfer complete The driver got an event for the setup phase, and passed the URB back. > [ 114.907052] usb-storage: Bulk command transfer result=0 > [ 114.907053] usb-storage: usb_stor_bulk_transfer_sglist: xfer 122880 bytes, 27 entries > [ 114.907054] xhci_hcd 0000:03:00.0: In xhci_handle_event > [ 114.907058] xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 64'hf8422038, 64'h3723618, 4'hf); Event ring dequeue pointer advances to 0x3723610. The event handler is done, so it writes a 1 to bit 3, which is the write-1-to-clear event handler busy bit. That's correct. > [ 114.907062] xhci_hcd 0000:03:00.0: count sg list trbs: > [ 114.907064] xhci_hcd 0000:03:00.0: sg #0: dma = 0xb21ca000, len = 0x3000 (12288), num_trbs = 1 > [ 114.907066] xhci_hcd 0000:03:00.0: sg #1: dma = 0xb21a2000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907068] xhci_hcd 0000:03:00.0: sg #2: dma = 0xb221a000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907071] xhci_hcd 0000:03:00.0: sg #3: dma = 0xb2186000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907073] xhci_hcd 0000:03:00.0: sg #4: dma = 0xb21a6000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907075] xhci_hcd 0000:03:00.0: sg #5: dma = 0xb221b000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907077] xhci_hcd 0000:03:00.0: sg #6: dma = 0xb2188000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907080] xhci_hcd 0000:03:00.0: sg #7: dma = 0xb2225000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907082] xhci_hcd 0000:03:00.0: sg #8: dma = 0xb2227000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907084] xhci_hcd 0000:03:00.0: sg #9: dma = 0xb2233000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907086] xhci_hcd 0000:03:00.0: sg #10: dma = 0xb2065000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907089] xhci_hcd 0000:03:00.0: sg #11: dma = 0xb216f000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907091] xhci_hcd 0000:03:00.0: sg #12: dma = 0xb214a000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907093] xhci_hcd 0000:03:00.0: sg #13: dma = 0xb2221000, len = 0x2000 (8192), num_trbs = 1 > [ 114.907096] xhci_hcd 0000:03:00.0: sg #14: dma = 0xb21a3000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907098] xhci_hcd 0000:03:00.0: sg #15: dma = 0xb20ee000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907100] xhci_hcd 0000:03:00.0: sg #16: dma = 0xb21fc000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907102] xhci_hcd 0000:03:00.0: sg #17: dma = 0xb21a0000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907104] xhci_hcd 0000:03:00.0: sg #18: dma = 0xb2182000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907107] xhci_hcd 0000:03:00.0: sg #19: dma = 0xb21ad000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907109] xhci_hcd 0000:03:00.0: sg #20: dma = 0xb276a000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907111] xhci_hcd 0000:03:00.0: sg #21: dma = 0xb2234000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907113] xhci_hcd 0000:03:00.0: sg #22: dma = 0xb2220000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907115] xhci_hcd 0000:03:00.0: sg #23: dma = 0xb21a5000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907118] xhci_hcd 0000:03:00.0: sg #24: dma = 0xb2189000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907120] xhci_hcd 0000:03:00.0: sg #25: dma = 0xb21fb000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907122] xhci_hcd 0000:03:00.0: sg #26: dma = 0xb2167000, len = 0x1000 (4096), num_trbs = 1 > [ 114.907124] xhci_hcd 0000:03:00.0: > [ 114.907126] usb 9-2: ep 0x1 - urb len = 122880, sglist used, num_trbs = 27 > [ 114.907127] xhci_hcd 0000:03:00.0: Endpoint state = 0x1 > [ 114.907129] xhci_hcd 0000:03:00.0: First length to xfer from 1st sglist entry = 12288 > [ 114.907131] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb21ca000, len = 0x3000 (12288), 64KB boundary at 0xb21d0000, end dma = 0xb21cd000 > [ 114.907133] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c120 (DMA) > [ 114.907136] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb21a2000, len = 0x1000 (4096), 64KB boundary at 0xb21b0000, end dma = 0xb21a3000 > [ 114.907138] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c130 (DMA) > [ 114.907140] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb221a000, len = 0x1000 (4096), 64KB boundary at 0xb2220000, end dma = 0xb221b000 > [ 114.907142] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c140 (DMA) > [ 114.907144] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb2186000, len = 0x1000 (4096), 64KB boundary at 0xb2190000, end dma = 0xb2187000 > [ 114.907146] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c150 (DMA) > [ 114.907148] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb21a6000, len = 0x1000 (4096), 64KB boundary at 0xb21b0000, end dma = 0xb21a7000 > [ 114.907150] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c160 (DMA) > [ 114.907152] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb221b000, len = 0x1000 (4096), 64KB boundary at 0xb2220000, end dma = 0xb221c000 > [ 114.907154] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c170 (DMA) > [ 114.907156] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb2188000, len = 0x1000 (4096), 64KB boundary at 0xb2190000, end dma = 0xb2189000 > [ 114.907158] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c180 (DMA) > [ 114.907160] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb2225000, len = 0x1000 (4096), 64KB boundary at 0xb2230000, end dma = 0xb2226000 > [ 114.907162] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c190 (DMA) > [ 114.907164] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb2227000, len = 0x1000 (4096), 64KB boundary at 0xb2230000, end dma = 0xb2228000 > [ 114.907166] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c1a0 (DMA) > [ 114.907168] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb2233000, len = 0x1000 (4096), 64KB boundary at 0xb2240000, end dma = 0xb2234000 > [ 114.907170] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c1b0 (DMA) > [ 114.907172] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb2065000, len = 0x1000 (4096), 64KB boundary at 0xb2070000, end dma = 0xb2066000 > [ 114.907174] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c1c0 (DMA) > [ 114.907177] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb216f000, len = 0x1000 (4096), 64KB boundary at 0xb2170000, end dma = 0xb2170000 > [ 114.907179] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c1d0 (DMA) > [ 114.907181] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb214a000, len = 0x1000 (4096), 64KB boundary at 0xb2150000, end dma = 0xb214b000 > [ 114.907182] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c1e0 (DMA) > [ 114.907184] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb2221000, len = 0x2000 (8192), 64KB boundary at 0xb2230000, end dma = 0xb2223000 > [ 114.907186] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c1f0 (DMA) > [ 114.907188] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb21a3000, len = 0x1000 (4096), 64KB boundary at 0xb21b0000, end dma = 0xb21a4000 > [ 114.907191] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c200 (DMA) > [ 114.907193] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb20ee000, len = 0x1000 (4096), 64KB boundary at 0xb20f0000, end dma = 0xb20ef000 > [ 114.907195] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c210 (DMA) > [ 114.907197] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb21fc000, len = 0x1000 (4096), 64KB boundary at 0xb2200000, end dma = 0xb21fd000 > [ 114.907199] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c220 (DMA) > [ 114.907201] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb21a0000, len = 0x1000 (4096), 64KB boundary at 0xb21b0000, end dma = 0xb21a1000 > [ 114.907203] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c230 (DMA) > [ 114.907205] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb2182000, len = 0x1000 (4096), 64KB boundary at 0xb2190000, end dma = 0xb2183000 > [ 114.907207] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c240 (DMA) > [ 114.907209] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb21ad000, len = 0x1000 (4096), 64KB boundary at 0xb21b0000, end dma = 0xb21ae000 > [ 114.907211] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c250 (DMA) > [ 114.907213] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb276a000, len = 0x1000 (4096), 64KB boundary at 0xb2770000, end dma = 0xb276b000 > [ 114.907215] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c260 (DMA) > [ 114.907217] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb2234000, len = 0x1000 (4096), 64KB boundary at 0xb2240000, end dma = 0xb2235000 > [ 114.907219] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c270 (DMA) > [ 114.907221] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb2220000, len = 0x1000 (4096), 64KB boundary at 0xb2230000, end dma = 0xb2221000 > [ 114.907223] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c280 (DMA) > [ 114.907225] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb21a5000, len = 0x1000 (4096), 64KB boundary at 0xb21b0000, end dma = 0xb21a6000 > [ 114.907227] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c290 (DMA) > [ 114.907229] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb2189000, len = 0x1000 (4096), 64KB boundary at 0xb2190000, end dma = 0xb218a000 > [ 114.907231] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c2a0 (DMA) > [ 114.907233] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb21fb000, len = 0x1000 (4096), 64KB boundary at 0xb2200000, end dma = 0xb21fc000 > [ 114.907235] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c2b0 (DMA) > [ 114.907237] xhci_hcd 0000:03:00.0: sg entry: dma = 0xb2167000, len = 0x1000 (4096), 64KB boundary at 0xb2170000, end dma = 0xb2168000 > [ 114.907239] xhci_hcd 0000:03:00.0: Ring enq = 0x3676c2c0 (DMA) > [ 114.907242] xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hf8423004, 32'h2, 4'hf); Here's the doorbell write for the data phase of the MSD command. Since this is a write MSD command, the data phase uses the same OUT endpoint, 0x01. You can see it's the same doorbell write as the last doorbell ring: > [ 114.906981] xhci_hcd 0000:03:00.0: `MEM_WRITE_DWORD(3'b000, 32'hf8423004, 32'h2, 4'hf); Then the host controller doesn't respond. The polling loop runs, which shows the last event was at 0x03723600, which was for the setup phase. You can tell by where the cycle bit (bit 0 of the fourth dword) is toggled. > [ 128.952013] xhci_hcd 0000:03:00.0: Poll event ring: 4294924533 > [ 128.952017] xhci_hcd 0000:03:00.0: op reg status = 0x0 > [ 128.952019] xhci_hcd 0000:03:00.0: ir_set 0 pending = 0x2 > [ 128.952021] xhci_hcd 0000:03:00.0: No-op commands handled = 0 > [ 128.952022] xhci_hcd 0000:03:00.0: HC error bitmask = 0x4 > [ 128.952024] xhci_hcd 0000:03:00.0: Event ring: > [ 128.952026] xhci_hcd 0000:03:00.0: @03723400 3676c490 00000000 01000000 01058000 > [ 128.952028] xhci_hcd 0000:03:00.0: @03723410 3676c000 00000000 01000000 01028000 > [ 128.952030] xhci_hcd 0000:03:00.0: @03723420 3676c4a0 00000000 01000000 01058000 > [ 128.952032] xhci_hcd 0000:03:00.0: @03723430 3676c010 00000000 01000000 01028000 > [ 128.952034] xhci_hcd 0000:03:00.0: @03723440 3676c020 00000000 01000000 01028000 > [ 128.952036] xhci_hcd 0000:03:00.0: @03723450 3676c4b0 00000000 01000000 01058000 > [ 128.952038] xhci_hcd 0000:03:00.0: @03723460 3676c030 00000000 01000000 01028000 > [ 128.952040] xhci_hcd 0000:03:00.0: @03723470 3676c4c0 00000000 01000000 01058000 > [ 128.952042] xhci_hcd 0000:03:00.0: @03723480 3676c040 00000000 01000000 01028000 > [ 128.952044] xhci_hcd 0000:03:00.0: @03723490 3676c4d0 00000000 01000000 01058000 > [ 128.952046] xhci_hcd 0000:03:00.0: @037234a0 3676c050 00000000 01000000 01028000 > [ 128.952048] xhci_hcd 0000:03:00.0: @037234b0 3676c4e0 00000000 01000000 01058000 > [ 128.952050] xhci_hcd 0000:03:00.0: @037234c0 3676c060 00000000 01000000 01028000 > [ 128.952052] xhci_hcd 0000:03:00.0: @037234d0 3676c4f0 00000000 01000000 01058000 > [ 128.952054] xhci_hcd 0000:03:00.0: @037234e0 3676c070 00000000 01000000 01028000 > [ 128.952056] xhci_hcd 0000:03:00.0: @037234f0 3676c500 00000000 01000000 01058000 > [ 128.952057] xhci_hcd 0000:03:00.0: @03723500 3676c080 00000000 01000000 01028000 > [ 128.952059] xhci_hcd 0000:03:00.0: @03723510 3676c510 00000000 01000000 01058000 > [ 128.952061] xhci_hcd 0000:03:00.0: @03723520 3676c090 00000000 01000000 01028000 > [ 128.952063] xhci_hcd 0000:03:00.0: @03723530 3676c520 00000000 01000000 01058000 > [ 128.952065] xhci_hcd 0000:03:00.0: @03723540 3676c0a0 00000000 01000000 01028000 > [ 128.952067] xhci_hcd 0000:03:00.0: @03723550 3676c530 00000000 01000000 01058000 > [ 128.952069] xhci_hcd 0000:03:00.0: @03723560 3676c0b0 00000000 01000000 01028000 > [ 128.952071] xhci_hcd 0000:03:00.0: @03723570 3676c540 00000000 01000000 01058000 > [ 128.952073] xhci_hcd 0000:03:00.0: @03723580 3676c0c0 00000000 01000000 01028000 > [ 128.952075] xhci_hcd 0000:03:00.0: @03723590 3676c550 00000000 01000000 01058000 > [ 128.952077] xhci_hcd 0000:03:00.0: @037235a0 3676c0d0 00000000 01000000 01028000 > [ 128.952079] xhci_hcd 0000:03:00.0: @037235b0 3676c560 00000000 01000000 01058000 > [ 128.952081] xhci_hcd 0000:03:00.0: @037235c0 3676c0e0 00000000 01000000 01028000 > [ 128.952083] xhci_hcd 0000:03:00.0: @037235d0 3676c570 00000000 01000000 01058000 > [ 128.952085] xhci_hcd 0000:03:00.0: @037235e0 3676c0f0 00000000 01000000 01028000 > [ 128.952087] xhci_hcd 0000:03:00.0: @037235f0 3676c580 00000000 01000000 01058000 > [ 128.952089] xhci_hcd 0000:03:00.0: @03723600 3676c100 00000000 01000000 01028000 <--- last event, setup phase > [ 128.952091] xhci_hcd 0000:03:00.0: @03723610 3676c780 00000000 01000000 01058001 > [ 128.952093] xhci_hcd 0000:03:00.0: @03723620 3676c300 00000000 01000000 01028001 > [ 128.952094] xhci_hcd 0000:03:00.0: @03723630 3676c790 00000000 01000000 01058001 > [ 128.952096] xhci_hcd 0000:03:00.0: @03723640 3676c7a0 00000000 01000000 01058001 > [ 128.952098] xhci_hcd 0000:03:00.0: @03723650 3676c310 00000000 01000000 01028001 > [ 128.952100] xhci_hcd 0000:03:00.0: @03723660 3676c7b0 00000000 01000000 01058001 > [ 128.952102] xhci_hcd 0000:03:00.0: @03723670 3676c320 00000000 01000000 01028001 > [ 128.952104] xhci_hcd 0000:03:00.0: @03723680 3676c7c0 00000000 01000000 01058001 > [ 128.952106] xhci_hcd 0000:03:00.0: @03723690 3676c330 00000000 01000000 01028001 > [ 128.952108] xhci_hcd 0000:03:00.0: @037236a0 3676c7d0 00000000 01000000 01058001 > [ 128.952110] xhci_hcd 0000:03:00.0: @037236b0 3676c340 00000000 01000000 01028001 > [ 128.952112] xhci_hcd 0000:03:00.0: @037236c0 3676c7e0 00000000 01000000 01058001 > [ 128.952114] xhci_hcd 0000:03:00.0: @037236d0 3676c350 00000000 01000000 01028001 > [ 128.952116] xhci_hcd 0000:03:00.0: @037236e0 3676c400 00000000 01000000 01058001 > [ 128.952118] xhci_hcd 0000:03:00.0: @037236f0 3676c360 00000000 01000000 01028001 > [ 128.952120] xhci_hcd 0000:03:00.0: @03723700 3676c410 00000000 01000000 01058001 > [ 128.952122] xhci_hcd 0000:03:00.0: @03723710 3676c370 00000000 01000000 01028001 > [ 128.952124] xhci_hcd 0000:03:00.0: @03723720 3676c420 00000000 01000000 01058001 > [ 128.952126] xhci_hcd 0000:03:00.0: @03723730 3676c380 00000000 01000000 01028001 > [ 128.952128] xhci_hcd 0000:03:00.0: @03723740 3676c430 00000000 01000000 01058001 > [ 128.952130] xhci_hcd 0000:03:00.0: @03723750 3676c390 00000000 01000000 01028001 > [ 128.952132] xhci_hcd 0000:03:00.0: @03723760 3676c440 00000000 01000000 01058001 > [ 128.952134] xhci_hcd 0000:03:00.0: @03723770 3676c3a0 00000000 01000000 01028001 > [ 128.952135] xhci_hcd 0000:03:00.0: @03723780 3676c450 00000000 01000000 01058001 > [ 128.952137] xhci_hcd 0000:03:00.0: @03723790 3676c3b0 00000000 01000000 01028001 > [ 128.952139] xhci_hcd 0000:03:00.0: @037237a0 3676c460 00000000 01000000 01058001 > [ 128.952141] xhci_hcd 0000:03:00.0: @037237b0 3676c3c0 00000000 01000000 01028001 > [ 128.952143] xhci_hcd 0000:03:00.0: @037237c0 3676c470 00000000 01000000 01058001 > [ 128.952145] xhci_hcd 0000:03:00.0: @037237d0 3676c3d0 00000000 01000000 01028001 > [ 128.952147] xhci_hcd 0000:03:00.0: @037237e0 3676c480 00000000 01000000 01058001 > [ 128.952149] xhci_hcd 0000:03:00.0: @037237f0 3676c3e0 00000000 01000000 01028001 > [ 128.952151] xhci_hcd 0000:03:00.0: Ring deq = c3723610 (virt), 0x3723610 (dma) > [ 128.952153] xhci_hcd 0000:03:00.0: Ring deq updated 23649 times > [ 128.952155] xhci_hcd 0000:03:00.0: Ring enq = c3723400 (virt), 0x3723400 (dma) > [ 128.952156] xhci_hcd 0000:03:00.0: Ring enq updated 0 times > [ 128.952160] xhci_hcd 0000:03:00.0: ERST deq = 64'h3723610 > [ 128.952161] xhci_hcd 0000:03:00.0: Command ring: > [ 128.952163] xhci_hcd 0000:03:00.0: @03723000 00000000 00000000 00000000 00002401 > [ 128.952165] xhci_hcd 0000:03:00.0: @03723010 367b1000 00000000 00000000 01002c01 > [ 128.952167] xhci_hcd 0000:03:00.0: @03723020 367b1000 00000000 00000000 01003001 > [ 128.952169] xhci_hcd 0000:03:00.0: @03723030 00000000 00000000 00000000 01013801 > [ 128.952171] xhci_hcd 0000:03:00.0: @03723040 367b1000 00000000 00000000 01003001 > [ 128.952173] xhci_hcd 0000:03:00.0: @03723050 00000000 00000000 00000000 00000000 > [ 128.952175] xhci_hcd 0000:03:00.0: @03723060 00000000 00000000 00000000 00000000 > [ 128.952176] xhci_hcd 0000:03:00.0: @03723070 00000000 00000000 00000000 00000000 > [ 128.952178] xhci_hcd 0000:03:00.0: @03723080 00000000 00000000 00000000 00000000 > [ 128.952180] xhci_hcd 0000:03:00.0: @03723090 00000000 00000000 00000000 00000000 > [ 128.952182] xhci_hcd 0000:03:00.0: @037230a0 00000000 00000000 00000000 00000000 > [ 128.952184] xhci_hcd 0000:03:00.0: @037230b0 00000000 00000000 00000000 00000000 > [ 128.952186] xhci_hcd 0000:03:00.0: @037230c0 00000000 00000000 00000000 00000000 > [ 128.952188] xhci_hcd 0000:03:00.0: @037230d0 00000000 00000000 00000000 00000000 > [ 128.952190] xhci_hcd 0000:03:00.0: @037230e0 00000000 00000000 00000000 00000000 > [ 128.952191] xhci_hcd 0000:03:00.0: @037230f0 00000000 00000000 00000000 00000000 > [ 128.952193] xhci_hcd 0000:03:00.0: @03723100 00000000 00000000 00000000 00000000 > [ 128.952195] xhci_hcd 0000:03:00.0: @03723110 00000000 00000000 00000000 00000000 > [ 128.952197] xhci_hcd 0000:03:00.0: @03723120 00000000 00000000 00000000 00000000 > [ 128.952199] xhci_hcd 0000:03:00.0: @03723130 00000000 00000000 00000000 00000000 > [ 128.952201] xhci_hcd 0000:03:00.0: @03723140 00000000 00000000 00000000 00000000 > [ 128.952203] xhci_hcd 0000:03:00.0: @03723150 00000000 00000000 00000000 00000000 > [ 128.952205] xhci_hcd 0000:03:00.0: @03723160 00000000 00000000 00000000 00000000 > [ 128.952206] xhci_hcd 0000:03:00.0: @03723170 00000000 00000000 00000000 00000000 > [ 128.952208] xhci_hcd 0000:03:00.0: @03723180 00000000 00000000 00000000 00000000 > [ 128.952210] xhci_hcd 0000:03:00.0: @03723190 00000000 00000000 00000000 00000000 > [ 128.952212] xhci_hcd 0000:03:00.0: @037231a0 00000000 00000000 00000000 00000000 > [ 128.952214] xhci_hcd 0000:03:00.0: @037231b0 00000000 00000000 00000000 00000000 > [ 128.952216] xhci_hcd 0000:03:00.0: @037231c0 00000000 00000000 00000000 00000000 > [ 128.952218] xhci_hcd 0000:03:00.0: @037231d0 00000000 00000000 00000000 00000000 > [ 128.952220] xhci_hcd 0000:03:00.0: @037231e0 00000000 00000000 00000000 00000000 > [ 128.952221] xhci_hcd 0000:03:00.0: @037231f0 00000000 00000000 00000000 00000000 > [ 128.952223] xhci_hcd 0000:03:00.0: @03723200 00000000 00000000 00000000 00000000 > [ 128.952225] xhci_hcd 0000:03:00.0: @03723210 00000000 00000000 00000000 00000000 > [ 128.952227] xhci_hcd 0000:03:00.0: @03723220 00000000 00000000 00000000 00000000 > [ 128.952229] xhci_hcd 0000:03:00.0: @03723230 00000000 00000000 00000000 00000000 > [ 128.952231] xhci_hcd 0000:03:00.0: @03723240 00000000 00000000 00000000 00000000 > [ 128.952233] xhci_hcd 0000:03:00.0: @03723250 00000000 00000000 00000000 00000000 > [ 128.952235] xhci_hcd 0000:03:00.0: @03723260 00000000 00000000 00000000 00000000 > [ 128.952236] xhci_hcd 0000:03:00.0: @03723270 00000000 00000000 00000000 00000000 > [ 128.952238] xhci_hcd 0000:03:00.0: @03723280 00000000 00000000 00000000 00000000 > [ 128.952240] xhci_hcd 0000:03:00.0: @03723290 00000000 00000000 00000000 00000000 > [ 128.952242] xhci_hcd 0000:03:00.0: @037232a0 00000000 00000000 00000000 00000000 > [ 128.952244] xhci_hcd 0000:03:00.0: @037232b0 00000000 00000000 00000000 00000000 > [ 128.952246] xhci_hcd 0000:03:00.0: @037232c0 00000000 00000000 00000000 00000000 > [ 128.952248] xhci_hcd 0000:03:00.0: @037232d0 00000000 00000000 00000000 00000000 > [ 128.952249] xhci_hcd 0000:03:00.0: @037232e0 00000000 00000000 00000000 00000000 > [ 128.952251] xhci_hcd 0000:03:00.0: @037232f0 00000000 00000000 00000000 00000000 > [ 128.952253] xhci_hcd 0000:03:00.0: @03723300 00000000 00000000 00000000 00000000 > [ 128.952255] xhci_hcd 0000:03:00.0: @03723310 00000000 00000000 00000000 00000000 > [ 128.952257] xhci_hcd 0000:03:00.0: @03723320 00000000 00000000 00000000 00000000 > [ 128.952259] xhci_hcd 0000:03:00.0: @03723330 00000000 00000000 00000000 00000000 > [ 128.952261] xhci_hcd 0000:03:00.0: @03723340 00000000 00000000 00000000 00000000 > [ 128.952263] xhci_hcd 0000:03:00.0: @03723350 00000000 00000000 00000000 00000000 > [ 128.952264] xhci_hcd 0000:03:00.0: @03723360 00000000 00000000 00000000 00000000 > [ 128.952266] xhci_hcd 0000:03:00.0: @03723370 00000000 00000000 00000000 00000000 > [ 128.952268] xhci_hcd 0000:03:00.0: @03723380 00000000 00000000 00000000 00000000 > [ 128.952270] xhci_hcd 0000:03:00.0: @03723390 00000000 00000000 00000000 00000000 > [ 128.952272] xhci_hcd 0000:03:00.0: @037233a0 00000000 00000000 00000000 00000000 > [ 128.952274] xhci_hcd 0000:03:00.0: @037233b0 00000000 00000000 00000000 00000000 > [ 128.952276] xhci_hcd 0000:03:00.0: @037233c0 00000000 00000000 00000000 00000000 > [ 128.952277] xhci_hcd 0000:03:00.0: @037233d0 00000000 00000000 00000000 00000000 > [ 128.952279] xhci_hcd 0000:03:00.0: @037233e0 00000000 00000000 00000000 00000000 > [ 128.952281] xhci_hcd 0000:03:00.0: @037233f0 03723000 00000000 00000000 00001802 > [ 128.952283] xhci_hcd 0000:03:00.0: Ring deq = c3723050 (virt), 0x3723050 (dma) > [ 128.952285] xhci_hcd 0000:03:00.0: Ring deq updated 5 times > [ 128.952286] xhci_hcd 0000:03:00.0: Ring enq = c3723050 (virt), 0x3723050 (dma) > [ 128.952288] xhci_hcd 0000:03:00.0: Ring enq updated 5 times > [ 128.952292] xhci_hcd 0000:03:00.0: // xHC command ring deq ptr low bits + flags = @00000008 > [ 128.952293] xhci_hcd 0000:03:00.0: // xHC command ring deq ptr high bits = @00000000 > [ 128.952295] xhci_hcd 0000:03:00.0: Dev 1 endpoint ring 0: > [ 128.952298] xhci_hcd 0000:03:00.0: @03723800 01000680 00080000 00000008 00000841 > [ 128.952300] xhci_hcd 0000:03:00.0: @03723810 367d3c80 00000000 00000008 00010c05 > [ 128.952302] xhci_hcd 0000:03:00.0: @03723820 00000000 00000000 00000000 00001021 > [ 128.952304] xhci_hcd 0000:03:00.0: @03723830 01000680 00120000 00000008 00000841 > [ 128.952306] xhci_hcd 0000:03:00.0: @03723840 030c08c0 00000000 00000012 00010c05 > [ 128.952308] xhci_hcd 0000:03:00.0: @03723850 00000000 00000000 00000000 00001021 > [ 128.952310] xhci_hcd 0000:03:00.0: @03723860 02000680 00090000 00000008 00000841 > [ 128.952312] xhci_hcd 0000:03:00.0: @03723870 037e3da0 00000000 00000009 00010c05 > [ 128.952313] xhci_hcd 0000:03:00.0: @03723880 00000000 00000000 00000000 00001021 > [ 128.952315] xhci_hcd 0000:03:00.0: @03723890 02000680 00200000 00000008 00000841 > [ 128.952317] xhci_hcd 0000:03:00.0: @037238a0 030c08c0 00000000 00000020 00010c05 > [ 128.952319] xhci_hcd 0000:03:00.0: @037238b0 00000000 00000000 00000000 00001021 > [ 128.952321] xhci_hcd 0000:03:00.0: @037238c0 03000680 00ff0000 00000008 00000841 > [ 128.952323] xhci_hcd 0000:03:00.0: @037238d0 35cbcf00 00000000 000000ff 00010c05 > [ 128.952325] xhci_hcd 0000:03:00.0: @037238e0 00000000 00000000 00000000 00001021 > [ 128.952327] xhci_hcd 0000:03:00.0: @037238f0 03020680 00ff0409 00000008 00000841 > [ 128.952329] xhci_hcd 0000:03:00.0: @03723900 35cbcf00 00000000 000000ff 00010c05 > [ 128.952331] xhci_hcd 0000:03:00.0: @03723910 00000000 00000000 00000000 00001021 > [ 128.952333] xhci_hcd 0000:03:00.0: @03723920 03010680 00ff0409 00000008 00000841 > [ 128.952335] xhci_hcd 0000:03:00.0: @03723930 35cbcf00 00000000 000000ff 00010c05 > [ 128.952337] xhci_hcd 0000:03:00.0: @03723940 00000000 00000000 00000000 00001021 > [ 128.952339] xhci_hcd 0000:03:00.0: @03723950 03030680 00ff0409 00000008 00000841 > [ 128.952341] xhci_hcd 0000:03:00.0: @03723960 35cbcf00 00000000 000000ff 00010c05 > [ 128.952343] xhci_hcd 0000:03:00.0: @03723970 00000000 00000000 00000000 00001021 > [ 128.952345] xhci_hcd 0000:03:00.0: @03723980 00010900 00000000 00000008 00000841 > [ 128.952347] xhci_hcd 0000:03:00.0: @03723990 00000000 00000000 00000000 00011021 > [ 128.952349] xhci_hcd 0000:03:00.0: @037239a0 0000fea1 00010000 00000008 00000841 > [ 128.952351] xhci_hcd 0000:03:00.0: @037239b0 35cdc000 00000000 00000001 00010c05 > [ 128.952353] xhci_hcd 0000:03:00.0: @037239c0 00000000 00000000 00000000 00001021 > [ 128.952355] xhci_hcd 0000:03:00.0: @037239d0 00000000 00000000 00000000 00000000 > [ 128.952357] xhci_hcd 0000:03:00.0: @037239e0 00000000 00000000 00000000 00000000 > [ 128.952358] xhci_hcd 0000:03:00.0: @037239f0 00000000 00000000 00000000 00000000 > [ 128.952360] xhci_hcd 0000:03:00.0: @03723a00 00000000 00000000 00000000 00000000 > [ 128.952362] xhci_hcd 0000:03:00.0: @03723a10 00000000 00000000 00000000 00000000 > [ 128.952364] xhci_hcd 0000:03:00.0: @03723a20 00000000 00000000 00000000 00000000 > [ 128.952366] xhci_hcd 0000:03:00.0: @03723a30 00000000 00000000 00000000 00000000 > [ 128.952368] xhci_hcd 0000:03:00.0: @03723a40 00000000 00000000 00000000 00000000 > [ 128.952370] xhci_hcd 0000:03:00.0: @03723a50 00000000 00000000 00000000 00000000 > [ 128.952372] xhci_hcd 0000:03:00.0: @03723a60 00000000 00000000 00000000 00000000 > [ 128.952373] xhci_hcd 0000:03:00.0: @03723a70 00000000 00000000 00000000 00000000 > [ 128.952375] xhci_hcd 0000:03:00.0: @03723a80 00000000 00000000 00000000 00000000 > [ 128.952377] xhci_hcd 0000:03:00.0: @03723a90 00000000 00000000 00000000 00000000 > [ 128.952379] xhci_hcd 0000:03:00.0: @03723aa0 00000000 00000000 00000000 00000000 > [ 128.952381] xhci_hcd 0000:03:00.0: @03723ab0 00000000 00000000 00000000 00000000 > [ 128.952383] xhci_hcd 0000:03:00.0: @03723ac0 00000000 00000000 00000000 00000000 > [ 128.952385] xhci_hcd 0000:03:00.0: @03723ad0 00000000 00000000 00000000 00000000 > [ 128.952387] xhci_hcd 0000:03:00.0: @03723ae0 00000000 00000000 00000000 00000000 > [ 128.952389] xhci_hcd 0000:03:00.0: @03723af0 00000000 00000000 00000000 00000000 > [ 128.952390] xhci_hcd 0000:03:00.0: @03723b00 00000000 00000000 00000000 00000000 > [ 128.952392] xhci_hcd 0000:03:00.0: @03723b10 00000000 00000000 00000000 00000000 > [ 128.952394] xhci_hcd 0000:03:00.0: @03723b20 00000000 00000000 00000000 00000000 > [ 128.952396] xhci_hcd 0000:03:00.0: @03723b30 00000000 00000000 00000000 00000000 > [ 128.952398] xhci_hcd 0000:03:00.0: @03723b40 00000000 00000000 00000000 00000000 > [ 128.952400] xhci_hcd 0000:03:00.0: @03723b50 00000000 00000000 00000000 00000000 > [ 128.952402] xhci_hcd 0000:03:00.0: @03723b60 00000000 00000000 00000000 00000000 > [ 128.952404] xhci_hcd 0000:03:00.0: @03723b70 00000000 00000000 00000000 00000000 > [ 128.952406] xhci_hcd 0000:03:00.0: @03723b80 00000000 00000000 00000000 00000000 > [ 128.952407] xhci_hcd 0000:03:00.0: @03723b90 00000000 00000000 00000000 00000000 > [ 128.952409] xhci_hcd 0000:03:00.0: @03723ba0 00000000 00000000 00000000 00000000 > [ 128.952411] xhci_hcd 0000:03:00.0: @03723bb0 00000000 00000000 00000000 00000000 > [ 128.952413] xhci_hcd 0000:03:00.0: @03723bc0 00000000 00000000 00000000 00000000 > [ 128.952415] xhci_hcd 0000:03:00.0: @03723bd0 00000000 00000000 00000000 00000000 > [ 128.952417] xhci_hcd 0000:03:00.0: @03723be0 00000000 00000000 00000000 00000000 > [ 128.952419] xhci_hcd 0000:03:00.0: @03723bf0 03723800 00000000 00000000 00001802 Here's the endpoint ring for ep 0x01: > [ 128.952420] xhci_hcd 0000:03:00.0: Dev 1 endpoint ring 1: > [ 128.952423] xhci_hcd 0000:03:00.0: @3676c000 35cdc000 00000000 0000001f 00000424 > [ 128.952425] xhci_hcd 0000:03:00.0: @3676c010 35cdc000 00000000 0000001f 00000424 > [ 128.952426] xhci_hcd 0000:03:00.0: @3676c020 35903200 00000000 00000200 00000424 > [ 128.952428] xhci_hcd 0000:03:00.0: @3676c030 35cdc000 00000000 0000001f 00000424 > [ 128.952430] xhci_hcd 0000:03:00.0: @3676c040 35cdc000 00000000 0000001f 00000424 > [ 128.952432] xhci_hcd 0000:03:00.0: @3676c050 35cdc000 00000000 0000001f 00000424 > [ 128.952434] xhci_hcd 0000:03:00.0: @3676c060 35cdc000 00000000 0000001f 00000424 > [ 128.952436] xhci_hcd 0000:03:00.0: @3676c070 35cdc000 00000000 0000001f 00000424 > [ 128.952438] xhci_hcd 0000:03:00.0: @3676c080 35cdc000 00000000 0000001f 00000424 > [ 128.952440] xhci_hcd 0000:03:00.0: @3676c090 35cdc000 00000000 0000001f 00000424 > [ 128.952442] xhci_hcd 0000:03:00.0: @3676c0a0 35cdc000 00000000 0000001f 00000424 > [ 128.952444] xhci_hcd 0000:03:00.0: @3676c0b0 35cdc000 00000000 0000001f 00000424 > [ 128.952446] xhci_hcd 0000:03:00.0: @3676c0c0 35cdc000 00000000 0000001f 00000424 > [ 128.952448] xhci_hcd 0000:03:00.0: @3676c0d0 35cdc000 00000000 0000001f 00000424 > [ 128.952450] xhci_hcd 0000:03:00.0: @3676c0e0 35cdc000 00000000 0000001f 00000424 > [ 128.952452] xhci_hcd 0000:03:00.0: @3676c0f0 35cdc000 00000000 0000001f 00000424 > [ 128.952453] xhci_hcd 0000:03:00.0: @3676c100 35cdc000 00000000 0000001f 00000424 ^^^ Setup phase, which we did get an event for. offset 0x00 and 0x04 - data buffer lo and high - 0x35cdc000 offset 0x08 - 0:16 transfer buffer length - 31 bytes, 21:17 - TD size is zero, meaning it's less than 1024 bytes (see explanation below). 31:22 - interrupter target 0 offset 0x0c - cycle bit cleared, interrupt on short packet set, chain bit cleared to show this is the only TRB in this TD, interrupt on completion set, TRB type is a normal TRB. That one looks fine. > [ 128.952455] xhci_hcd 0000:03:00.0: @3676c110 b21ca000 00000000 00303000 00000414 buffer 0xb21ca000, 0x3000 bytes to be transferred. TD size is 0x18, or 24. TD size is supposed to be the number of bytes remaining (including the current TRB), right shifted by 10. If that's bigger than 31, the driver is supposed to set it to 31. The scatter gather list is 122880 bytes long. (122880 >> 10) = 120, so that field should be set to 31, but it's not. It's this silly macro's fault: #define TD_REMAINDER(p) ((((p) >> 10) & 0x1f) << 17) It should return 31 if p is bigger than 32767, but it doesn't. (((122880) >> 10) & 0x1f) = 24, which is consistent with your output. I'll send you a patch to fix it shortly. Sarah > [ 128.952457] xhci_hcd 0000:03:00.0: @3676c120 b21a2000 00000000 00181000 00000414 > [ 128.952459] xhci_hcd 0000:03:00.0: @3676c130 b221a000 00000000 00101000 00000414 > [ 128.952461] xhci_hcd 0000:03:00.0: @3676c140 b2186000 00000000 00081000 00000414 > [ 128.952463] xhci_hcd 0000:03:00.0: @3676c150 b21a6000 00000000 00001000 00000414 > [ 128.952465] xhci_hcd 0000:03:00.0: @3676c160 b221b000 00000000 00381000 00000414 > [ 128.952467] xhci_hcd 0000:03:00.0: @3676c170 b2188000 00000000 00301000 00000414 > [ 128.952469] xhci_hcd 0000:03:00.0: @3676c180 b2225000 00000000 00281000 00000414 > [ 128.952471] xhci_hcd 0000:03:00.0: @3676c190 b2227000 00000000 00201000 00000414 > [ 128.952473] xhci_hcd 0000:03:00.0: @3676c1a0 b2233000 00000000 00181000 00000414 > [ 128.952475] xhci_hcd 0000:03:00.0: @3676c1b0 b2065000 00000000 00101000 00000414 > [ 128.952477] xhci_hcd 0000:03:00.0: @3676c1c0 b216f000 00000000 00081000 00000414 > [ 128.952479] xhci_hcd 0000:03:00.0: @3676c1d0 b214a000 00000000 00001000 00000414 > [ 128.952481] xhci_hcd 0000:03:00.0: @3676c1e0 b2221000 00000000 00382000 00000414 > [ 128.952483] xhci_hcd 0000:03:00.0: @3676c1f0 b21a3000 00000000 00281000 00000414 > [ 128.952485] xhci_hcd 0000:03:00.0: @3676c200 b20ee000 00000000 00201000 00000414 > [ 128.952487] xhci_hcd 0000:03:00.0: @3676c210 b21fc000 00000000 00181000 00000414 > [ 128.952489] xhci_hcd 0000:03:00.0: @3676c220 b21a0000 00000000 00101000 00000414 > [ 128.952491] xhci_hcd 0000:03:00.0: @3676c230 b2182000 00000000 00081000 00000414 > [ 128.952493] xhci_hcd 0000:03:00.0: @3676c240 b21ad000 00000000 00001000 00000414 > [ 128.952495] xhci_hcd 0000:03:00.0: @3676c250 b276a000 00000000 00381000 00000414 > [ 128.952497] xhci_hcd 0000:03:00.0: @3676c260 b2234000 00000000 00301000 00000414 > [ 128.952499] xhci_hcd 0000:03:00.0: @3676c270 b2220000 00000000 00281000 00000414 > [ 128.952501] xhci_hcd 0000:03:00.0: @3676c280 b21a5000 00000000 00201000 00000414 > [ 128.952503] xhci_hcd 0000:03:00.0: @3676c290 b2189000 00000000 00181000 00000414 > [ 128.952505] xhci_hcd 0000:03:00.0: @3676c2a0 b21fb000 00000000 00101000 00000414 > [ 128.952506] xhci_hcd 0000:03:00.0: @3676c2b0 b2167000 00000000 00081000 00000424 <--- cycle bit toggle, last entry for data phase > [ 128.952508] xhci_hcd 0000:03:00.0: @3676c2c0 35cdc000 00000000 0000001f 00000425 > [ 128.952510] xhci_hcd 0000:03:00.0: @3676c2d0 35cdc000 00000000 0000001f 00000425 > [ 128.952512] xhci_hcd 0000:03:00.0: @3676c2e0 35cdc000 00000000 0000001f 00000425 > [ 128.952514] xhci_hcd 0000:03:00.0: @3676c2f0 35cdc000 00000000 0000001f 00000425 > [ 128.952516] xhci_hcd 0000:03:00.0: @3676c300 35cdc000 00000000 0000001f 00000425 > [ 128.952518] xhci_hcd 0000:03:00.0: @3676c310 35cdc000 00000000 0000001f 00000425 > [ 128.952520] xhci_hcd 0000:03:00.0: @3676c320 35cdc000 00000000 0000001f 00000425 > [ 128.952522] xhci_hcd 0000:03:00.0: @3676c330 35cdc000 00000000 0000001f 00000425 > [ 128.952524] xhci_hcd 0000:03:00.0: @3676c340 35cdc000 00000000 0000001f 00000425 > [ 128.952526] xhci_hcd 0000:03:00.0: @3676c350 35cdc000 00000000 0000001f 00000425 > [ 128.952528] xhci_hcd 0000:03:00.0: @3676c360 35cdc000 00000000 0000001f 00000425 > [ 128.952530] xhci_hcd 0000:03:00.0: @3676c370 35cdc000 00000000 0000001f 00000425 > [ 128.952532] xhci_hcd 0000:03:00.0: @3676c380 35cdc000 00000000 0000001f 00000425 > [ 128.952533] xhci_hcd 0000:03:00.0: @3676c390 35cdc000 00000000 0000001f 00000425 > [ 128.952535] xhci_hcd 0000:03:00.0: @3676c3a0 35cdc000 00000000 0000001f 00000425 > [ 128.952537] xhci_hcd 0000:03:00.0: @3676c3b0 35cdc000 00000000 0000001f 00000425 > [ 128.952539] xhci_hcd 0000:03:00.0: @3676c3c0 35cdc000 00000000 0000001f 00000425 > [ 128.952541] xhci_hcd 0000:03:00.0: @3676c3d0 35cdc000 00000000 0000001f 00000425 > [ 128.952543] xhci_hcd 0000:03:00.0: @3676c3e0 35cdc000 00000000 0000001f 00000425 > [ 128.952545] xhci_hcd 0000:03:00.0: @3676c3f0 3676c000 00000000 00000000 00001803 -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
