Dear Experts,
Does anyone understand how the "nak count reload" feature in EHCI works?
I have an embedded system with a PCI bus connecting the processor to a
USB host controller and some other peripherals. The bandwidth of this
bus is rather poor and I would like to minimise the amount used by the
USB controller. It seems that when it is polling e.g. a bulk IN
endpoint it does quite a lot of PCI activity in order to access its
schedule data structures, even if no USB data is actually transferred.
I would like to reduce the frequency of polling in this case.
Looking at the EHCI spec, I have found a feature called "nak count
reload" that may do what I want. AFAICS, the Linux EHCI driver
[warning, old kernel!] sets this to 4. I have the impression that this
should allow me to introduce some sort of pause after 4 consecutive
Naks. However, I get lost is a maze of twisty spec suibsections, all
different, at this point. So can anyone help me understand what is
supposed to happen, and what I can adjust, after those 4 Naks?
Many thanks,
Phil.
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