Re: Anyone understand Nak count reload?

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On Wed, 2 Sep 2009, Phil Endecott wrote:

> Dear Experts,
> 
> Does anyone understand how the "nak count reload" feature in EHCI works?

Yes.  :-)

> I have an embedded system with a PCI bus connecting the processor to a 
> USB host controller and some other peripherals.  The bandwidth of this 
> bus is rather poor and I would like to minimise the amount used by the 
> USB controller.  It seems that when it is polling e.g. a bulk IN 
> endpoint it does quite a lot of PCI activity in order to access its 
> schedule data structures, even if no USB data is actually transferred.  
> I would like to reduce the frequency of polling in this case.
> 
> Looking at the EHCI spec, I have found a feature called "nak count 
> reload" that may do what I want.  AFAICS, the Linux EHCI driver 
> [warning, old kernel!] sets this to 4.  I have the impression that this 
> should allow me to introduce some sort of pause after 4 consecutive 
> Naks.

That's basically right.

>  However, I get lost is a maze of twisty spec suibsections, all 
> different, at this point.  So can anyone help me understand what is 
> supposed to happen, and what I can adjust, after those 4 Naks?

What is supposed to happen is that the controller decides the endpoint
is temporarily inactive when the NAK counter reaches 0.  When all the
endpoints on the async schedule are inactive, the controller pauses the
schedule for a little while (around 10 us).  Then it restarts the whole
procedure, reloading the NAK counters from the RL fields.

You cannot control the duration of this pause; it is built into the 
controller hardware.

You can reduce the initial count from 4 down to 1 (or anything in
between).  The value used by ehci-hcd is given by the EHCI_TUNE_RL_HS
symbol near the start of ehci-hcd.c.  If you are using full/low-speed
devices attached through a high-speed hub, you should also set
EHCI_TUNE_RL_TT to a nonzero value.

Alan Stern

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