Re: [PATCH 4/4] EHCI: Support Intel Moorestown EHCI controller SRAM as DMA pool caching

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



On Thu, Jun 11, 2009 at 07:28:17PM +0800, Alek Du wrote:
> From f3c088f9e609a54140498cce27f6f12f737c870b Mon Sep 17 00:00:00 2001
> From: Jacob Pan <jacob.jun.pan@xxxxxxxxx>
> Date: Wed, 20 May 2009 14:41:55 +0800
> Subject: [PATCH] EHCI: Support Intel Moorestown EHCI controller SRAM as DMA pool caching
> 
> The Intel Moorestown platform has MPH and OTG EHCI controllers that
> have Internal SRAM could be used as QH/QTD/ITD/SITD DMA pool caching.
> The SRAM are exposed via PCI BAR1. The limitation here is the SRAM
> access should be 32bit aligned. A separate patch "EHCI: Make ehci_qh
> structure items all 32bit aligned" has been submitted to linux-usb
> mailling list.
> 
> Signed-off-by: Jacob Pan <jacob.jun.pan@xxxxxxxxx>
> Signed-off-by: Alek Du <alek.du@xxxxxxxxx>
> ---
>  drivers/usb/core/buffer.c   |    5 +++++
>  drivers/usb/core/hcd.h      |    1 +
>  drivers/usb/host/ehci-hcd.c |    9 ++++++++-
>  drivers/usb/host/ehci-pci.c |   39 +++++++++++++++++++++++++++++++++++++++
>  drivers/usb/host/ehci.h     |    8 +++++++-
>  5 files changed, 60 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/usb/core/buffer.c b/drivers/usb/core/buffer.c
> index 3ba2fff..ab0f462 100644
> --- a/drivers/usb/core/buffer.c
> +++ b/drivers/usb/core/buffer.c
> @@ -115,6 +115,11 @@ void *hcd_buffer_alloc(
>  		return kmalloc(size, mem_flags);
>  	}
>  
> +	/* we won't use internal SRAM as data payload, we can't get
> +	   any benefits from it */
> +	if (hcd->has_sram)
> +		return dma_alloc_coherent(NULL, size, dma, mem_flags);
> +
>  	for (i = 0; i < HCD_BUFFER_POOLS; i++) {
>  		if (size <= pool_max [i])
>  			return dma_pool_alloc(hcd->pool [i], mem_flags, dma);
> diff --git a/drivers/usb/core/hcd.h b/drivers/usb/core/hcd.h
> index e7d4479..696fcf2 100644
> --- a/drivers/usb/core/hcd.h
> +++ b/drivers/usb/core/hcd.h
> @@ -104,6 +104,7 @@ struct usb_hcd {
>  	unsigned		wireless:1;	/* Wireless USB HCD */
>  	unsigned		authorized_default:1;
>  	unsigned		has_tt:1;	/* Integrated TT in root hub */
> +	unsigned		has_sram:1;	/* Local SRAM for caching */
>  
>  	int			irq;		/* irq allocated */
>  	void __iomem		*regs;		/* device memory/io */
> diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
> index 31122e0..d37de6b 100644
> --- a/drivers/usb/host/ehci-hcd.c
> +++ b/drivers/usb/host/ehci-hcd.c
> @@ -106,6 +106,12 @@ static int ignore_oc = 0;
>  module_param (ignore_oc, bool, S_IRUGO);
>  MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
>  
> +static unsigned int sram_force_off;
> +module_param(sram_force_off, int, S_IRUGO);
> +MODULE_PARM_DESC(sram_force_off,
> +		"force private SRAM off, otherwise SRAM will be used"
> +		"if detected\n");

Ick, no.  Can't you detect this in the hardware and do it dynamically?
We don't need any more configuration options.  Especially something as
vague and undocumented as this.

So no, please don't do this.

thanks,

greg k-h
--
To unsubscribe from this list: send the line "unsubscribe linux-usb" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[Index of Archives]     [Linux Media]     [Linux Input]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]     [Old Linux USB Devel Archive]

  Powered by Linux