Re: pxa27x_udc and pxa3xx compatibility

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Eric Miao <eric.y.miao@xxxxxxxxx> writes:

>> PS: Aric, would you retest that patch, as I transformed "a bit" your original
>> work, and confirm your "Signed-off-by" stills holds for that patch please ?
>>
>
> Well, for Aric's patch below, my comment is that this also holds true for
> pxa27x, so the if (cpu_is_pxa3xx()) isn't really necessary. We have to
> clear OPC on both pxa27x and pxa3xx for this.

Well, I'll make some tests anew.

I put that comment into pxa27x_udc at development time :
 *   - clearing UDCCSR0_OPC always flushes ep0. If in setup stage, never do it
 *     before reading ep0.

IIRC, clearing OPC for ep0 could "destroy" the incoming setup packet.

Now, I see your point : if OPC is set _and_ bytes count in ep0 fifo is 0, then
we can safely clear OPC.

But do we have the guarantee that clearing OPC will fill in "immediately" the
ep0 fifo with the 2 bytes of the SETUP packet ? If not, the FSM should be
amended, to get out of handle_ep0_ctrl_request(), so that the next ep0 irq
raised on the "true" setup packet will take care of the setup.

Anyway, I'll repass the test, and rethink the patch a bit ...

Cheers.

--
Robert
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