Hi, On Tuesday 24 February 2009 00:17:22 Sebastian Andrzej Siewior wrote: > According to section 14.1.3, table 95 write - read delay is 195ns for > EHCI op regs and the SKIPMAP register is one of those see table 8 in > section 8. So the required delay should be 195ns. This constraint > probably fails on fast boxes if we enqueue a following qtd-packet for > the same urb in the interrupt handler. Yes. I use 1760 with a 530 MHz Blackfin, and I am having the same problem. > | If we get called from the interrupt handler to enqueue a follow-up > | packet the SKIP register gets written and read again almost > | immediately. This register requires a delay of 195ns before a read can > | happen after a write, see section 14.1.3 Hmmm.... are you sure? I think that the 195ns are valid not for individual registers, but for all EHCI op regs. So if you access register A, you have to wait 195ns until you can access register B. Maybe the best solution is to add a special delay_ehci_op() primitive and handle the delay inside the primitive (platform-specific?). I am still not sure how to add a 195 ns delay. Maybe access some other 1760 registers and count on the minimum access timing of the 1760? regards Wolfgang -- Wahre Worte sind nicht schön. Schöne Worte sind nicht wahr. (Laotse) -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
