[HELP] USB 3.0 PCI Endpoint problem

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Hi to all!
I am testing a PCIe Root Complex prototyping setup in which I have a USB 3.0
host as a PCI Endpoint.
Running in an ARC CPU platform it works well, but when running in an emulated
ARM64 (this is done by a Synopsys virtualization tool) the endpoint
initialization fails as can be seen in the following log:

xhci_hcd 0000:01:00.0: xHCI Host Controller
xhci_hcd 0000:01:00.0: new USB bus registered, assigned bus number 1
xhci_hcd 0000:01:00.0: xHCI capability registers at ffffff80002c4000:
xhci_hcd 0000:01:00.0: CAPLENGTH AND HCIVERSION 0x960020:
xhci_hcd 0000:01:00.0: CAPLENGTH: 0x20
xhci_hcd 0000:01:00.0: HCIVERSION: 0x96
xhci_hcd 0000:01:00.0: HCSPARAMS 1: 0x4000820
xhci_hcd 0000:01:00.0:   Max device slots: 32
xhci_hcd 0000:01:00.0:   Max interrupters: 8
xhci_hcd 0000:01:00.0:   Max ports: 4
xhci_hcd 0000:01:00.0: HCSPARAMS 2: 0x11
xhci_hcd 0000:01:00.0:   Isoc scheduling threshold: 1
xhci_hcd 0000:01:00.0:   Maximum allowed segments in event ring: 1
xhci_hcd 0000:01:00.0: HCSPARAMS 3 0x0:
xhci_hcd 0000:01:00.0:   Worst case U1 device exit latency: 0
xhci_hcd 0000:01:00.0:   Worst case U2 device exit latency: 0
xhci_hcd 0000:01:00.0: HCC PARAMS 0x14042cb:
xhci_hcd 0000:01:00.0:   HC generates 64 bit addresses
xhci_hcd 0000:01:00.0:   FIXME: more HCCPARAMS debugging
xhci_hcd 0000:01:00.0: RTSOFF 0x600:
xhci_hcd 0000:01:00.0: xHCI operational registers at ffffff80002c4020:
xhci_hcd 0000:01:00.0: USBCMD 0x0:
xhci_hcd 0000:01:00.0:   HC is being stopped
xhci_hcd 0000:01:00.0:   HC has finished hard reset
xhci_hcd 0000:01:00.0:   Event Interrupts disabled
xhci_hcd 0000:01:00.0:   Host System Error Interrupts disabled
xhci_hcd 0000:01:00.0:   HC has finished light reset
xhci_hcd 0000:01:00.0: USBSTS 0x9:
xhci_hcd 0000:01:00.0:   Event ring is not empty
xhci_hcd 0000:01:00.0:   No Host System Error
xhci_hcd 0000:01:00.0:   HC is halted
xhci_hcd 0000:01:00.0: ffffff80002c4420 port status reg = 0x2a0
xhci_hcd 0000:01:00.0: ffffff80002c4424 port power reg = 0x0
xhci_hcd 0000:01:00.0: ffffff80002c4428 port link reg = 0x0
xhci_hcd 0000:01:00.0: ffffff80002c442c port reserved reg = 0x0
xhci_hcd 0000:01:00.0: ffffff80002c4430 port status reg = 0x2a0
xhci_hcd 0000:01:00.0: ffffff80002c4434 port power reg = 0x0
xhci_hcd 0000:01:00.0: ffffff80002c4438 port link reg = 0x0
xhci_hcd 0000:01:00.0: ffffff80002c443c port reserved reg = 0x0
xhci_hcd 0000:01:00.0: ffffff80002c4440 port status reg = 0x2a0
xhci_hcd 0000:01:00.0: ffffff80002c4444 port power reg = 0x0
xhci_hcd 0000:01:00.0: ffffff80002c4448 port link reg = 0x0
xhci_hcd 0000:01:00.0: ffffff80002c444c port reserved reg = 0x0
xhci_hcd 0000:01:00.0: ffffff80002c4450 port status reg = 0x2a0
xhci_hcd 0000:01:00.0: ffffff80002c4454 port power reg = 0x0
xhci_hcd 0000:01:00.0: ffffff80002c4458 port link reg = 0x0
xhci_hcd 0000:01:00.0: ffffff80002c445c port reserved reg = 0x0
xhci_hcd 0000:01:00.0: // Halt the HC
xhci_hcd 0000:01:00.0: Resetting HCD
xhci_hcd 0000:01:00.0: // Reset the HC
xhci_hcd 0000:01:00.0: Wait for controller to be ready for doorbell rings
xhci_hcd 0000:01:00.0: Reset complete
xhci_hcd 0000:01:00.0: Enabling 64-bit DMA addresses.
xhci_hcd 0000:01:00.0: Calling HCD init
xhci_hcd 0000:01:00.0: xhci_init
xhci_hcd 0000:01:00.0: xHCI doesn't need link TRB QUIRK
xhci_hcd 0000:01:00.0: Supported page size register = 0x1
xhci_hcd 0000:01:00.0: Supported page size of 4K
xhci_hcd 0000:01:00.0: HCD page size set to 4K
xhci_hcd 0000:01:00.0: // xHC can handle at most 32 device slots.
xhci_hcd 0000:01:00.0: // Setting Max device slots reg = 0x20.
xhci_hcd 0000:01:00.0: // Device context base array address = 0xfcafb000 (DMA),
ffffff80002c7000 (virt)
xhci_hcd 0000:01:00.0: Allocated command ring at ffffffc07db28cc0
xhci_hcd 0000:01:00.0: First segment DMA is 0xfc42c000
xhci_hcd 0000:01:00.0: // Setting command ring address to 0x20
xhci_hcd 0000:01:00.0: // xHC command ring deq ptr low bits + flags = @00000000
xhci_hcd 0000:01:00.0: // xHC command ring deq ptr high bits = @00000000
xhci_hcd 0000:01:00.0: // Doorbell array is located at offset 0x800 from cap
regs base addr
xhci_hcd 0000:01:00.0: // xHCI capability registers at ffffff80002c4000:
xhci_hcd 0000:01:00.0: // @ffffff80002c4000 = 0x960020 (CAPLENGTH AND HCIVERSION)
xhci_hcd 0000:01:00.0: //   CAPLENGTH: 0x20
xhci_hcd 0000:01:00.0: // xHCI operational registers at ffffff80002c4020:
xhci_hcd 0000:01:00.0: // @ffffff80002c4018 = 0x600 RTSOFF
xhci_hcd 0000:01:00.0: // xHCI runtime registers at ffffff80002c4600:
xhci_hcd 0000:01:00.0: // @ffffff80002c4014 = 0x800 DBOFF
xhci_hcd 0000:01:00.0: // Doorbell array at ffffff80002c4800:
xhci_hcd 0000:01:00.0: xHCI runtime registers at ffffff80002c4600:
xhci_hcd 0000:01:00.0:   ffffff80002c4600: Microframe index = 0x0
xhci_hcd 0000:01:00.0: // Allocating event ring
xhci_hcd 0000:01:00.0: TRB math tests passed.
xhci_hcd 0000:01:00.0: // Allocated event ring segment table at 0xfc42e000
xhci_hcd 0000:01:00.0: Set ERST to 0; private num segs = 1, virt addr =
ffffff80002cd000, dma addr = 0xfc42e000
xhci_hcd 0000:01:00.0: // Write ERST size = 1 to ir_set 0 (some bits preserved)
xhci_hcd 0000:01:00.0: // Set ERST entries to point to event ring.
xhci_hcd 0000:01:00.0: // Set ERST base address for ir_set 0 = 0xfc42e000
xhci_hcd 0000:01:00.0: // Write event ring dequeue pointer, preserving EHB bit
xhci_hcd 0000:01:00.0: Wrote ERST address to ir_set 0.
xhci_hcd 0000:01:00.0: Allocating 0 scratchpad buffers
xhci_hcd 0000:01:00.0: Ext Cap ffffff80002c4510, port offset = 1, count = 2,
revision = 0x3
xhci_hcd 0000:01:00.0: Ext Cap ffffff80002c4520, port offset = 3, count = 2,
revision = 0x2
xhci_hcd 0000:01:00.0: Found 2 USB 2.0 ports and 2 USB 3.0 ports.
xhci_hcd 0000:01:00.0: USB 2.0 port at index 2, addr = ffffff80002c4440
xhci_hcd 0000:01:00.0: USB 2.0 port at index 3, addr = ffffff80002c4450
xhci_hcd 0000:01:00.0: USB 3.0 port at index 0, addr = ffffff80002c4420
xhci_hcd 0000:01:00.0: USB 3.0 port at index 1, addr = ffffff80002c4430
xhci_hcd 0000:01:00.0: Reading op_regs->dev_notification
xhci_hcd 0000:01:00.0: Reading finished: 0
xhci_hcd 0000:01:00.0: Writting op_regs->dev_notification: 2
xhci_hcd 0000:01:00.0: Writting finished: 2
xhci_hcd 0000:01:00.0: Finished xhci_init
xhci_hcd 0000:01:00.0: Called HCD init
xhci_hcd 0000:01:00.0: xhci_run
xhci_hcd 0000:01:00.0: Command ring memory map follows:
xhci_hcd 0000:01:00.0: @00000000fc42c000 00000000 00000000 00000000 00000000
(...)
xhci_hcd 0000:01:00.0: @00000000fc42c3f0 fc42c000 00000000 00000000 00001802
xhci_hcd 0000:01:00.0:   Ring has not been updated
xhci_hcd 0000:01:00.0: Ring deq = ffffff80002c9000 (virt), 0xfc42c000 (dma)
xhci_hcd 0000:01:00.0: Ring deq updated 0 times
xhci_hcd 0000:01:00.0: Ring enq = ffffff80002c9000 (virt), 0xfc42c000 (dma)
xhci_hcd 0000:01:00.0: Ring enq updated 0 times
xhci_hcd 0000:01:00.0: // xHC command ring deq ptr low bits + flags = @00000000
xhci_hcd 0000:01:00.0: // xHC command ring deq ptr high bits = @00000000
xhci_hcd 0000:01:00.0: ERST memory map follows:
xhci_hcd 0000:01:00.0: @00000000fc42e000 fc42c400 00000000 00000040 00000000
xhci_hcd 0000:01:00.0: Event ring:
xhci_hcd 0000:01:00.0: @00000000fc42c400 00000000 00000000 00000000 00000000
(...)
xhci_hcd 0000:01:00.0: @00000000fc42c7f0 00000000 00000000 00000000 00000000
xhci_hcd 0000:01:00.0:   Ring has not been updated
xhci_hcd 0000:01:00.0: Ring deq = ffffff80002c9400 (virt), 0xfc42c400 (dma)
xhci_hcd 0000:01:00.0: Ring deq updated 0 times
xhci_hcd 0000:01:00.0: Ring enq = ffffff80002c9400 (virt), 0xfc42c400 (dma)
xhci_hcd 0000:01:00.0: Ring enq updated 0 times
xhci_hcd 0000:01:00.0: ERST deq = 64'hfc42c400
xhci_hcd 0000:01:00.0: // Set the interrupt modulation register
xhci_hcd 0000:01:00.0: // Enable interrupts, cmd = 0x4.
xhci_hcd 0000:01:00.0: // Enabling event ring interrupter ffffff80002c4620 by
writing 0x2 to irq_pending
xhci_hcd 0000:01:00.0:   ffffff80002c4620: ir_set[0]
xhci_hcd 0000:01:00.0:   ffffff80002c4620: ir_set.pending = 0x2
xhci_hcd 0000:01:00.0:   ffffff80002c4624: ir_set.control = 0xa0
xhci_hcd 0000:01:00.0:   ffffff80002c4628: ir_set.erst_size = 0x1
xhci_hcd 0000:01:00.0:   ffffff80002c4630: ir_set.erst_base = @fc42e000
xhci_hcd 0000:01:00.0:   ffffff80002c4638: ir_set.erst_dequeue = @fc42c400
xhci_hcd 0000:01:00.0: Finished xhci_run for USB2 roothub
xHCI xhci_add_endpoint called for root hub
xHCI xhci_check_bandwidth called for root hub
xhci_hcd 0000:01:00.0: Endpoint 0x81 ep reset callback called
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 2 ports detected
xhci_hcd 0000:01:00.0: set port power, actual port 0 status  = 0x2a0
xhci_hcd 0000:01:00.0: set port power, actual port 1 status  = 0x2a0
xhci_hcd 0000:01:00.0: xHCI Host Controller
xhci_hcd 0000:01:00.0: new USB bus registered, assigned bus number 2
xhci_hcd 0000:01:00.0: Entered xhci_run_finished
xhci_hcd 0000:01:00.0: // Turn on HC, cmd = 0x5.
xhci_hcd 0000:01:00.0: // xHCI operational registers (Status): 0:
xhci_hcd 0000:01:00.0: // Ding dong!
xhci_hcd 0000:01:00.0: Finished xhci_run for USB3 roothub
xHCI xhci_add_endpoint called for root hub
xHCI xhci_check_bandwidth called for root hub
xhci_hcd 0000:01:00.0: Endpoint 0x81 ep reset callback called
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 2 ports detected
xhci_hcd 0000:01:00.0: set port power, actual port 0 status  = 0x2a0
xhci_hcd 0000:01:00.0: set port power, actual port 1 status  = 0x2a0
xhci_hcd 0000:01:00.0: get port status, actual port 0 status  = 0x2a0
xhci_hcd 0000:01:00.0: Get port status returned 0x100
xhci_hcd 0000:01:00.0: get port status, actual port 1 status  = 0x2a0
xhci_hcd 0000:01:00.0: Get port status returned 0x100
xhci_hcd 0000:01:00.0: get port status, actual port 0 status  = 0x2a0
xhci_hcd 0000:01:00.0: Get port status returned 0x2a0
xhci_hcd 0000:01:00.0: get port status, actual port 1 status  = 0x2a0
xhci_hcd 0000:01:00.0: Get port status returned 0x2a0
xhci_hcd 0000:01:00.0: Command timeout
xhci_hcd 0000:01:00.0: Abort command ring

Apparently the USB 2.0 part seems ok, but the USb 3.0 part fails because of a
command timeout. I have increased a lot the cmd_timer expires but nothing
changed. Can anyone give me an hint?

Thanks,
Joao



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