Thanks Joe, for the confirmation. Thanks Mathias for the update. Raj -----Original Message----- From: Mathias Nyman [mailto:mathias.nyman@xxxxxxxxxxxxxxx] Sent: Wednesday, October 21, 2015 3:15 AM To: Joe Lawrence; linux-usb@xxxxxxxxxxxxxxx; Mani, Rajmohan Subject: Re: [PATCH] xhci: Workaround to get Intel xHCI reset working more reliably On 19.10.2015 17:37, Joe Lawrence wrote: > On 10/16/2015 03:29 AM, Rajmohan Mani wrote: >> From: Rajmohan Mani <rajmohan.mani@xxxxxxxxx> >> >> Existing Intel xHCI controllers require a delay of 1 mS, after >> setting the CMD_RESET bit in command register, before accessing any >> HC registers. This allows the HC to complete the reset operation and >> be ready for HC register access. >> Without this delay, the subsequent HC register access, may result in >> a system hang, very rarely. >> >> Verified CherryView / Braswell platforms go through over >> 5000 warm reboot cycles (which was not possible without this patch), >> without any xHCI reset hang. >> >> Signed-off-by: Rajmohan Mani <rajmohan.mani@xxxxxxxxx> > Hi Rajmohan, > > Thanks for looking into this XHCI reset quirk. We ran this patch on a > Stratus FT machine and it successfully reset ~1500 times over the > weekend without any issue. > > Feel free to add: > > Tested-by: Joe Lawrence <joe.lawrence@xxxxxxxxxxx> > Thanks for the patch. Added the Tested-by tag and queued the patch Will go forward to 4.4-rc1 -Mathias ��.n��������+%������w��{.n�����{���)�� jg��� �����ݢj����G���� ���j:+v���w�m������w�������h�����٥
