Hi, On Mon, Oct 20, 2014 at 11:38:23PM +0800, Huang Rui wrote: > On Fri, Oct 17, 2014 at 10:10:26AM -0500, Felipe Balbi wrote: > > Hi, > > > > On Fri, Oct 17, 2014 at 04:53:25PM +0800, Huang Rui wrote: > > > The series of patches add AMD NL SoC support for DesignWare USB3 OTG > > > IP with PCI bus glue layer. This controller supported hibernation, LPM > > > erratum and used the 2.80a IP version and amd own phy. Current > > > implementation support both simulation and SoC platform. And already > > > tested with gadget zero and msc tool. It works well on file storage > > > gadget. > > > > patches look much, much nicer there are still a few things to fix. A > > global set of issues which I see: > > > > 1) Let's get confirmation that all those quirks will be needed in > > production as well, I have a feeling quite a few of them won't be. > > > > 2) All quirks should become 1-bit fields insteads of single-bits on a > > 32-bit variable. > > > > 3) All quirks should have DeviceTree counterparts. They should all > > become boolean properties should we can: > > > > dwc->tx_deemphasis_quirk = of_property_read_bool(node, > > "snps,tx_deemphasis_quirk"); > > > > Thanks to summarize them. Will update in V3. hey, no problem. > > > These patches are generated on balbi/testing/next > > > > > > Changes from v1 -> v2 > > > - remove dual role function temporarily > > > - add pci quirk to avoid to bind with xhci driver > > > - distinguish between simulation board and soc > > > - break down all the special quirks > > > > > > > > > Patch 1: > > > - add PCI device id into pci bus glue > > > > this guy should be the last in the series, with all AMD quirks being > > enabled at once. This will avoid bisection points where AMD's platforms > > don't work. > > > > So all the AMD special configuration and device id should be in one > patch, right? correct :-) -- balbi
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