On Wed, Aug 25, 2021 at 9:23 AM Baruch Siach <baruch@xxxxxxxxxx> wrote: > > Hi Rob, > > On Wed, Aug 25 2021, Rob Herring wrote: > > On Wed, Aug 25, 2021 at 6:25 AM Baruch Siach <baruch@xxxxxxxxxx> wrote: > >> On Fri, Aug 06 2021, Rob Herring wrote: > >> > On Wed, May 5, 2021 at 3:18 AM Baruch Siach <baruch@xxxxxxxxxx> wrote: > >> >> + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + > >> >> + PCI_EXP_DEVCTL2); > >> >> + > >> >> + writel(PCIE_CAP_CURR_DEEMPHASIS | SPEED_GEN3, > >> >> + pci->dbi_base + offset + PCI_EXP_DEVCTL2); > >> > > >> > Doesn't this overwrite the prior register write? > >> > >> It does. There are two mistakes here. The writel() above should set > >> PCIE20_DEVICE_CONTROL2_STATUS2 (offset 0x98). > > > > No. Did you check what 'offset' is? PCIE20_DEVICE_CONTROL2_STATUS2 is > > PCI_EXP_DEVCTL2 plus the status reg. What's wrong is it should be a > > 16-bit write. > > Thanks for enlightening me. 'offset' is 0x70 here. So PCI_EXP_DEVCTL2 is > at 0x98, and PCI_EXP_LNKCTL2 is at 0xa0. Only the second writel() is > wrong. But since generic code handles speed, I can drop it entirely. > > I see that dw_pcie_link_set_max_speed() uses dw_pcie_writel_dbi() to > write to PCI_EXP_LNKCTL2. Is that 16-bit write? No, that may be because some platforms can only do 32-bit accesses and dw_pcie_writew_dbi would be a RMW in that case. Or maybe there's some reliance on clearing the status register. > Why are pci_regs.h register offsets in decimal? No idea... Rob
