This series adds support for the single PCIe lane on IPQ6018 SoCs. The code is ported from downstream Codeaurora v5.4 kernel. The main difference from downstream code is the split of PCIe registers configuration from .init to .post_init, since it requires phy_power_on(). Tested on IPQ6010 based hardware. Changes in v2: * Add patch moving GEN3_RELATED macros to a common header * Drop ATU configuration from pcie-qcom * Remove local definition of common registers * Use bulk clk and reset APIs * Remove msi-parent from device-tree Baruch Siach (3): PCI: dwc: tegra: move GEN3_RELATED DBI register to common header dt-bindings: phy: qcom,qmp: Add IPQ60xx PCIe PHY bindings dt-bindings: pci: qcom: Document PCIe bindings for IPQ6018 SoC Selvam Sathappan Periakaruppan (3): PCI: qcom: add support for IPQ60xx PCIe controller phy: qcom-qmp: add QMP V2 PCIe PHY support for ipq60xx arm64: dts: ipq6018: Add pcie support .../devicetree/bindings/pci/qcom,pcie.txt | 24 +++ .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 25 +++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 99 ++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 7 + drivers/pci/controller/dwc/pcie-qcom.c | 150 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-tegra194.c | 6 - drivers/phy/qualcomm/phy-qcom-qmp.c | 147 +++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 132 +++++++++++++++ 8 files changed, 584 insertions(+), 6 deletions(-) -- 2.30.2
