On Fri, Mar 13, 2020 at 12:01:04PM +0300, Dmitry Osipenko wrote: > The PL310 Auxiliary Control Register shouldn't have the "Full line of > zero" optimization bit being set before L2 cache is enabled. The L2X0 > driver takes care of enabling the optimization by itself. > > This patch fixes a noisy error message on Tegra20 and Tegra30 telling > that cache optimization is erroneously enabled without enabling it for > the CPU: > > L2C-310: enabling full line of zeros but not enabled in Cortex-A9 > > Cc: <stable@xxxxxxxxxxxxxxx> > Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx> > --- > arch/arm/mach-tegra/tegra.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Applied to for-5.8/arm/core, thanks. Thierry
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