Le ven. 13 mars 2020 à 10:02, Dmitry Osipenko <digetx@xxxxxxxxx> a écrit : > > The PL310 Auxiliary Control Register shouldn't have the "Full line of > zero" optimization bit being set before L2 cache is enabled. The L2X0 > driver takes care of enabling the optimization by itself. > > This patch fixes a noisy error message on Tegra20 and Tegra30 telling > that cache optimization is erroneously enabled without enabling it for > the CPU: > > L2C-310: enabling full line of zeros but not enabled in Cortex-A9 > > Cc: <stable@xxxxxxxxxxxxxxx> > Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx> Tested-by: Nicolas Chauvet <kwizart@xxxxxxxxx> This was tested on paz00 (tegra20). Also tested that suspend still works. Thanks for fixing this long standing issue! -- - Nicolas (kwizart)
