On Thu, Mar 19, 2020 at 10:36:48PM +0300, Dmitry Osipenko wrote: > The memory clock-rate change could be running on a non-boot CPU, while the > boot CPU handles the EMC interrupt. This introduces an unnecessary latency > since boot CPU should handle the interrupt and then notify the sibling CPU > about clock-rate change completion. In some rare cases boot CPU could be > in uninterruptible state for a significant time (like in a case of KASAN + > NFS root), it could get to the point that completion timeouts before boot > CPU gets a chance to handle interrupt. The solution is to get rid of the > completion and replace it with interrupt-status polling. > > Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx> > --- > drivers/memory/tegra/tegra30-emc.c | 116 +++++++++++------------------ > 1 file changed, 44 insertions(+), 72 deletions(-) Applied to for-5.8/memory, thanks. Thierry
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