Re: Tegra 2: Spurious interrupts from UARTA (@70006000)

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On 06/13/2018 08:08 PM, Dmitry Osipenko wrote:
>> During the failure, somehow the interrupt continues to be triggered,
>> even though the IIR register shows no active interrupts (IIR == 0xC1)
>>
> Hello David,
>
> TRM says "IS_STA: Interrupt Pending if ZERO" for BIT(1) of UART_IIR_FCR_0
> register, this matches the UART standard that kernel follows by checking
> whether UART_IIR_NO_INT bit is set in the serial8250_handle_irq().
That bit is
> zero in your case, meaning that interrupt is asserted.
>

Hello Dmitry, thanks for your answer!

IIR is in my case 0xC1 == 1100.0001, so the lowest bit #0, IS_STA, has
the value 1. So the UART itself says, that no interrupt is there.
The table in the TRM is layed out ambiguous here, as the register really
corresponds to two registers: IIR (when reading) and FCR (when writing).
Sadly the table has interleaved rows for both registers, so you might
have mixed up the row numbering and thus the bit#?

Cheers,

David
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