On 06/13/2018 11:28 PM, Peter Geis wrote: > Good Evening David, > > Just to make sure, you have explicitly defined the functions for UARTA > and all spare functions right? > According to the TRM, if you don't have the functions explicitly > defined, and a function is assigned to both the primary and alternate > pingroups, or two functions assigned to the same pingroup, you can get > unpredictable behavior. Hi Peter, you are right, thats a good point. Actually, the Tegra2 CPU even has a silicon bug related to this, see https://patchwork.kernel.org/patch/3582721/ . That's why the 8250 driver (if recognizing a TEGRA port on a TEGRA2 CPU) disables the MSR interrupts, which can be triggered by any unconnected or wrongly muxed lines that are not RX and TX. Even when the functions are muxed to something else (!), and the IIR flag *would* be missing in that case, according to the above post. I made sure the MSR really is disabled by tracing all register accesses and dumping the registers at specific times. We also have 8 UART lines (DTR, CTS, RTS, DSR, DCD, RXD, TXD and RI) externally connected to a SN65C3243 (a dedicated RS232 line driver/receiver), which should take care of pulling the lines correctly. The schematic is exactly like the corresponding Toradex dev-board. So hardware-signals should be fine and pulled correctly. Makes sense, as all works fine using the old 3.1.x kernel by toradex/nvidia. As for the pin-muxing: We build upon the standard tegra20-colibri-512.dsti device tree, which sets the sdio1 group to Config 3, thus UART1. sdio1 correspond to six of the lines connected externally. The other two are DSR (connected to gpio C1, LCD_PWR1, group LPW1) and DCD (connected to gpio C6, LDC_PWR2, group LPW2). Those pins can both not be muxed to any UART1 function. LPW1 gets effectively tristated by our device tree overlay. Interestingly, LPW2 seems to be set to "displayb". A display signal on there might interfere with the core, though unlikely as we don't use the display interface. I will check that signal tomorrow and then also tristate it. As for any other pingroups that could be muxed to UART1: * GPU (GPIO_PU0 .. PU6) are used for the GMI interface. * IRRX, IRTX (UART2_RTS_N, UART2_CTS_N) are used for GMI. * SDB (SDIO3) is muxed for PWM * SDD (SDIO3) is muxed for PWM * UAA (ULPI_DATA0..DATA3) is muxed for ULPI * UAB (ULPI_DATA4..DATA7) is muxed for ULPI * UAD (UART2_RXD, UART2_TXD) is muxed for IRDA (i.e. UART2) So besides LPW2, nothing to go on. Thats at least one thing to go on :-) Sorry for the verbosity, but I double-checked everything and wanted to make sure I got it all correct. David -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
