On 03/02/2018 06:27 AM, Peter Geis wrote:
Good Morning,
I have an OUYA console that I am attempting to get the 4.14 kernel
booted on.
It is a Tegra30-Cardhu based system, which from what I can tell had as
many corners cut during development as possible.
I do not have access to the firmware itself, and the firmware does not
support anything beyond 3.1.10, so I am using a kernel appended DTB.
The issue I'm running into right now is I cannot get the layer 2 cache
controller, a PL310, to init correctly.
I can disable the function, and I boot till DMA starts accessing
hardware and go into a hard lock.
If I have the L2C enabled, it kernel panics during L2c310_configure,
while trying to write the secure registers.
I am pretty sure the firmware is not using secure mode at all, and in
the cache-l2x0.c source the function states "By default, we write
directly to secure registers. Platforms must override this if they are
running non-secure."
You can tell whether SW is running in secure mode; see below. This will
tell you whether (a) there's just some general bug, or (b) the kernel is
running in non-secure mode and needs adjustment to do so, since that's
probably not currently supported.
To find out how to tell, see the following code in U-Boot:
http://git.denx.de/?p=u-boot.git;a=blob;f=arch/arm/mach-tegra/board.c;h=b3a041b539af80ae7b75e3f709931ab92ff1a213;hb=refs/heads/master#l52
While that is only validated on Tegra124, I expect it works the same on
Tegra30. The PMC address and/or mc_security_cfg0 register offset might
need to be adjusted though; track down the definitions for both chips in
U-Boot's header files to check.
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