On Mon, Feb 29, 2016 at 09:46:07PM +0100, Lucas Stach wrote: > The post divider value in the frequency table is wrong as it > would lead to the PLL producing a output rate of 960MHz instead > of the desired 480MHz. This wasn't a problem as nothing used the > table to actually init the PLL rate, but the bootloader > configuration was used unaltered. > > If the bootloader does not set up the PLL it will fail to come > when used under Linux. To fix this don't rely on the bootloader, > but set the correct rate in the clock driver. > > Signed-off-by: Lucas Stach <dev@xxxxxxxxxx> > --- > drivers/clk/tegra/clk-tegra30.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) Applied, thanks. Thierry
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