Am Montag, den 29.02.2016, 21:46 +0100 schrieb Lucas Stach:
> If the bootloader does not touch PLL_C it will stay in its reset
> state, failing to lock when enabled. This leads to consumers of
> this clock to fail probing. Fix this by always programming the
> PLL with a sane rate, which allows it to lock, at startup.
>
Those 2 patches haven't been applied, as far as I can see. Any comments
on them?
> Signed-off-by: Lucas Stach <dev@xxxxxxxxxx>
> ---
> drivers/clk/tegra/clk-tegra30.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-
> tegra30.c
> index 0478565..236e2db 100644
> --- a/drivers/clk/tegra/clk-tegra30.c
> +++ b/drivers/clk/tegra/clk-tegra30.c
> @@ -1372,6 +1372,7 @@ static struct tegra_clk_init_table init_table[]
> __initdata = {
> { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 },
> { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 },
> { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
> + { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
> { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 },
> { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 },
> { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 },
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