On Wed, Jul 09, 2014 at 03:43:44PM +0300, Peter De Schrijver wrote: > On Wed, Jul 09, 2014 at 02:04:02PM +0200, Thierry Reding wrote: > > > For those 2 domains we can find the necessary clocks and resets by parsing > > > the relevant existing DT nodes for PCIe and gr3d. For clocks, this isn't > > > even needed as we can always register some extra clkdev's to get them. There > > > is no equivalent for resets so we have to parse the gr3d and pcie DT nodes, > > > but that's not too bad I think. > > > > Even if we could really do this, at this point I don't see an advantage. > > All that it would be doing is move to some subsystem that doesn't quite > > match what we need just for the sake of moving to that subsystem. Having > > a Tegra-specific API doesn't sound so bad anymore. > > > > The advantage would be that we can use LP0/SC7 as a cpuidle state. How is that going to work? And why does it need powergates to be implemented as power domains? If we switch off power gates, then we need to restore context in the drivers anyway, therefore I assume .suspend() and .resume() would need to be called, in which case powergate handling can surely be done at that stage, can't it? > Also system > resume from LP0 can be faster as we potentially don't have to resume all > domains at once. I don't understand what that's got to do with anything. If we call into the PMC driver explicitly via tegra_powergate_*() functions from driver code, then we have full control over suspend/resume in the drivers, and therefore don't need to resume all at once either. Thierry
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