On Wed, 2012-10-31 at 06:27 +0800, Stephen Warren wrote: > On 10/30/2012 04:03 PM, Antti P Miettinen wrote: > > Joseph Lo <josephl@xxxxxxxxxx> writes: > >>>>>> + writel(tegra_in_lp2.bits[0], tegra_cpu_lp2_mask); > > > > BTW, writel_relaxed() would probably be more than enough? IRAM is mapped > > stronly ordered, isn't it? And there's an explicit dsb(). And the mask > > is observed and written only by CPUs. If there are coherence issues, > > they would be in the fabric? And then neither CPU barriers nor L2 sync > > would help, you'd need a readback, right? > > I expect there are many places where we simply default to using > readl/writel (e.g. due to cut/paste, their prevalence, etc.) rather than > explicitly using the _relaxed variants if we can. Perhaps we should do a > pass through all the Tegra code and clean that up sometime. Hi Antti, Thanks for review. I had updated this code from V2. The code looks like below right now. It's similar to "writel_relaxed" function. And I had verified this code in SMP environment it can sync the status of "cpu_in_lp2". I don't see any coherency issue in IRAM memory space right now. I knew some IO registers that under PPSB bus (peripheral bus) needed a readback as a barrier. Because PPSB queues write transactions. I had verified this on Tegra20 & Tegra30. It's reliable. *cpu_in_lp2 |= BIT(phy_cpu_id); or *cpu_in_lp2 &= ~BIT(phy_cpu_id); Thanks, Joseph -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
