Joseph Lo <josephl@xxxxxxxxxx> writes: >> >>> + writel(tegra_in_lp2.bits[0], tegra_cpu_lp2_mask); BTW, writel_relaxed() would probably be more than enough? IRAM is mapped stronly ordered, isn't it? And there's an explicit dsb(). And the mask is observed and written only by CPUs. If there are coherence issues, they would be in the fabric? And then neither CPU barriers nor L2 sync would help, you'd need a readback, right? -- Antti P Miettinen http://www.iki.fi/~ananaza/ -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
