Re: High CPU load when using MAX14830 SPI UART controller

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The MAX14830 supports also another mode of operation where the interrupt fires only when the RX buffer gets filled over a configurable minimal threshold. This can be combined with yet another interrupt which fires whenever there's some data in the RX FIFO for "too long". Unfortunately, this timer starts over again upon reception of any additional data, so it's the *youngest* byte in the RX FIFO that controls triggering of this delayed interrupt.

Do you have some more details about this mode of operation? I looked a
bit at the MAX14830 datasheet and code, but couldn't spot what allows
an interrupt to be triggered after X bytes have been received *OR* if
data has been sitting in the FIFO for too long.

I have no code, but according to the datasheet, it's the "RTimeout" bit (Line Status Register, bit 0). If properly configured (RxTimeOut set and the interrupt routing enabled via LSRIntEn[0], the "RTimeoutIEn" bit), we're supposed to get ISR[0] set upon this timeout.

I have not tried it, I just read the datasheet a few years ago. When you have patches, I'll be happy to test them (likely only in September, though, because of vacations).

With kind regards,
Jan




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