Re: [PATCH] spi: xilinx: Add DT support for selecting transfer word width

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On Tue, Oct 22, 2019 at 02:06:11PM +0200, Alvaro Gamez Machado wrote:
> On Tue, Oct 22, 2019 at 12:26:00PM +0100, Mark Brown wrote:

> > This is still something that should be configured by the client driver,
> > if you send data with a different word size to that the client intends
> > it'll just get corrupted.

> The problem is that Xilinx's AXI Quad SPI core doesn't allow this. When
> instantiating the core you must choose *the* transfer width, not the
> *maximum* transfer width. So in my example above, no matter how I configure
> my IP core, linux'll believe that its datawidth is 8. I could override it
> hardcoding a 32 in spi-xilinx.c, but then what would happen with my other
> IP core that needs a datawidth of 8? Client code cannot configure IP core
> with a different datawidth because it simply does not allow it.

If the SPI controller can't cope with sending anything but 32 bits
that's fine, the slave still needs to know that it's supposed to be
handing the host controller data laid out in 32 bit words.  All the
components need to agree about how the data is supposed to be
interpreted.

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