Re: [PATCH 0/7] Raspberry Pi spi0 improvements

[Lukas Wunner <lukas@xxxxxxxxx>]

On Tue, Nov 13, 2018 at 09:12:01PM -0800, Florian Fainelli wrote:
> On 11/7/2018 11:06 PM, Lukas Wunner wrote:
> > Here's a first batch of improvements for the spi0 master on the
> > Raspberry Pi.  The meat of the series is in its last two patches:
> > 
> > * Patch [6/7] allows DMA for transfer buffers starting at an offset not a
> >   multiple of 4.  This overcomes a limitation affecting Ethernet drivers
> >   such as ks8851 which call netdev_alloc_skb_ip_align() to allocate
> >   deliberately unaligned receive buffers.
> > 
> > * Patch [7/7] speeds up PIO transfers by not polling the RX FIFO when it
> >   is known to contain data, or the TX FIFO when it is known to have free
> >   space.
> 
> Do you have some performance numbers that you could share before/after,
> e.g: transfer latencies, number of interrupts and pure throughput?

The throughput is primarily determined by the serial clock configured in
the DT for a specific SPI slave.  There's nothing we can improve there
in software.

This series is about reducing CPU usage.  E.g. without patch [6/7],
transfer buffers not aligned to 32-bit are transmitted with programmed I/O
instead of DMA.  Thus, constantly receiving packets on a ks8851 Ethernet
chip with a serial clock of 20 MHz occupies 25% of a CPU on a RasPi 3
(for the ks8851 IRQ thread).  With the patch, it drops to a negligible
percentage.  The spi-bcm2835.c driver currently forces PIO even for
kmalloc'ed buffers which are always contiguous in physical memory,
i.e. for no reason at all.

Patch [7/7] likewise reduces CPU usage, it skips unnecessary MMIO reads.
That doesn't make a huge difference but with a traffic-intensive chip
such as the ks8851, every little bit helps.

Thanks,

Lukas