On Wed, Jul 20, 2016 at 12:41:11PM -0700, Florian Fainelli wrote: > Now, as to whether it makes sense to model the IDM enable/disable > (intr_regs resource) and the 7 32-bits interrupt status/acknowledge > words at the end of the MSPI+BSPI block (intr_status_regs resource) as > an interrupt controller makes sense or not, it is kind of hard to say, > because really the IDM IO_CONTROL aggregates more than just interrupt > enable/disable bits here, but the overall ownership of this IDM > IO_CONTROL is clear and it belongs to the SPI function of the system. TBH if that's all it's doing then I'm surprised it's not simple to handle it with irq_setup_generic_chip() - have you looked at that at all?
Attachment:
signature.asc
Description: PGP signature
