Re: [PATCH, V4, 2/5] spi: bcm-qspi: Add SPI flash and MSPI driver

[Kamal Dasu <kdasu.kdev@xxxxxxxxx>]

Mark,

On Fri, Jul 1, 2016 at 12:07 PM, Mark Brown <broonie@xxxxxxxxxx> wrote:
> On Fri, Jul 01, 2016 at 11:39:03AM -0400, Kamal Dasu wrote:
>
>> > All this interrupt code and especially the fact that it's a completely
>> > separate register range in the binding looks very much like it's just
>> > an interrupt controller IP that's not particularly anything to do with
>> > the SPI controller and should therefore be in a separate driver.  Why is
>> > this part of the SPI controller driver?
>
>> Some SoCs need this since they do not implement a separate interrupt
>> controller and have dedicated l1 interrupt for spi. Also the handling
>> is not generic enough to cover other ips as well in those case. Hence
>> have to handle it within the driver.
>
> That doesn't seem to match what the code is actually doing.  The
> register block this is controlling is separate to the rest of the IP.
> It's perfectly OK to have a driver for an interrupt controller which is
> only used in one place, though you may find one of the generic ones
> might be able to handle it anyway.
>

The NS* SoC  SPI blocks has hw glue logic specific to MSPI+BSPI, so
the re-usability of an interrupt controller driver for this  logic is
limited.  The spi only (spi protocol) block does use l2 controller,
however for the MSPI+BSPI block used for the spi-nor flash had to
introduce the code to handle l1 interrupts within the code itself. In
this case can the driver be accepted without having to introduce a new
intc driver ?.

Thanks
Kamal
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