On Fri, Mar 20, 2015 at 03:10:04PM +0200, Peter Ujfalusi wrote: > On 03/19/2015 08:51 PM, Mark Brown wrote: > > You probably need both - there's often a hard limit where the FIFO size > > in the hardware becomes a limit for DMA as well as a soft limit on top > > of that for performance reasons. > The FIFO is only going to be enabled when the DMA is used for transfer so we > should have some lower limit for the PIO/DMA threshold. The FIFO in McSPI is a Right, that's pretty much what I'm trying to say. > tricky one anyways, since it has only one FIFO but several channels and the > FIFO can be enabled for only one channel, if it is enabled for more channels > it is not going to be used by either channel. Not sure I follow this - how does this whole multiple channels thing work for SPI exactly?
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