On Tue, Nov 25, 2014 at 05:30:04AM -0800, Andrey Smirnov wrote: > > No, that's not the case at all. A spi_transfer can have a length that's > > an unsigned integer number of bytes which is much larger than 255 bits. > > What is the actual problem you're trying to solve here? I suspect the > > driver you are using is just badly implemented... > Yes, and you're absolutely right about spi_transfer, however I wasn't > talking about spi_transfer at all. My point was about SPI transaction > which is all the bits shifted out on the bus(and shifted in as well) > during the duration of the CS/SS signal assertion. A spi_message (which is the thing that covers the entire /CS assert modulo non-standard fiddling) is composed of multiple spi_transfers so the above still applies... > >> + if (!u_tmp->bits_per_word && u_tmp->bits_per_burst) > >> + k_tmp->bits_per_word = u_tmp->bits_per_burst; > >> + else > >> + k_tmp->bits_per_word = u_tmp->bits_per_word; > > This is setting the number of bits per word which is nothing to do with > > FIFOs or the lengths of transfers but instead concerns the formatting of > > data onto the bus. > I don't believe I said that this commit had anything to do with FIFO. > I did acknowledge that fact that modern SoC have large FIFO and this > is relevant because often times the size of that FIFO is what > determines the size of a single SPI transaction. I tried to be careful No it doesn't, chip select can frequently be manipulated independently of data transfers and almost all controllers can support transfers much longer than their FIFOs either by doing that or by keeping the FIFO topped up during transfer. > in my wording of the summary and not use the word "transfer" anywhere, > but it looks like I slipped twice and that might have contributed to > this confusion. I apologize for this and hope that my comments > clarified my meaning/intent Sorry it's still not at all clear, please re-read what I wrote about what bits_per_word means since I really don't think you've understood what it's for.
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