> -----Original Message-----
> From: Jiri Slaby <jirislaby@xxxxxxxxxx>
> Sent: 2022年10月24日 14:37
> To: Sherry Sun <sherry.sun@xxxxxxx>; gregkh@xxxxxxxxxxxxxxxxxxx;
> lukas@xxxxxxxxx; ilpo.jarvinen@xxxxxxxxxxxxxxx
> Cc: linux-serial@xxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; dl-linux-imx
> <linux-imx@xxxxxxx>
> Subject: Re: [PATCH V3] tty: serial: fsl_lpuart: don't break the on-going
> transfer when global reset
>
> On 20. 10. 22, 15:19, Sherry Sun wrote:
> > @@ -2636,6 +2610,54 @@ static const struct serial_rs485
> lpuart_rs485_supported = {
> > /* delay_rts_* and RX_DURING_TX are not supported */
> > };
> >
> > +static int lpuart_global_reset(struct lpuart_port *sport) {
> > + struct uart_port *port = &sport->port;
> > + void __iomem *global_addr;
> > + unsigned long ctrl, bd;
> > + unsigned int val = 0;
> > + int ret;
> > +
> > + ret = clk_prepare_enable(sport->ipg_clk);
> > + if (ret) {
> > + dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n",
> ret);
> > + return ret;
> > + }
> > +
> > + if (is_imx7ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
> > + /*
> > + * If the transmitter is used by earlycon, wait for transmit
> engine to
> > + * complete and then reset.
> > + */
> > + ctrl = lpuart32_read(port, UARTCTRL);
> > + if (ctrl & UARTCTRL_TE) {
> > + bd = lpuart32_read(&sport->port, UARTBAUD);
> > + if (read_poll_timeout_atomic(lpuart32_tx_empty, val,
> val, 1, 100000,
> > + false, port)) {
>
> Ah, this is not atomic context (clk_prepare_enable() above and
> usleep_range() below), so no need for _atomic here too.
>
Hi Jiri,
You are right, thanks for the correction, will fix it in V4.
Best Regards
Sherry
