Hi Geert-san,
Thank you for your review!
> From: Geert Uytterhoeven, Sent: Thursday, April 21, 2022 10:48 PM
>
> Hi Shimoda-san,
>
> On Wed, Apr 20, 2022 at 10:43 AM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@xxxxxxxxxxx> wrote:
> > R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
>
> Thanks for your patch!
>
> > ---
> > drivers/clk/renesas/r8a779f0-cpg-mssr.c | 18 +++++++++---------
> > drivers/clk/renesas/rcar-gen4-cpg.c | 5 +++++
> > drivers/clk/renesas/rcar-gen4-cpg.h | 3 +++
> > 3 files changed, 17 insertions(+), 9 deletions(-)
>
> You forgot to update drivers/clk/renesas/r8a779a0-cpg-mssr.c.
I completely forgot it. I'll fix it.
> Hence all clocks derived from PLL5 have a zero rate, causing the
> SDHI driver to enter an infinite loop in renesas_sdhi_set_clock()
> (clock = 0):
>
> for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
> clock <<= 1;
>
> Adding the missing PLL4 mul/div columns fixes that.
I got it.
> The rest LGTM.
Thank you for your review!
Best regards,
Yoshihiro Shimoda
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
