On Wed, Mar 30, 2022 at 03:20:37PM +0200, Miquel Raynal wrote:
> From: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
>
> Renesas RZ/N1 SoC features a slightly modified DW UART.
>
> On this SoC, the CPR register value is known but not synthetized in
> hardware. We hence need to provide a CPR value in the platform
> data. This version of the controller also relies on acting as flow
> controller when using DMA, so we need to provide the
> "is dma flow controller" quirk.
After modifying one of previous patches...
> Signed-off-by: Phil Edworthy <phil.edworthy@xxxxxxxxxxx>
> Co-developed-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx>
> Signed-off-by: Miquel Raynal <miquel.raynal@xxxxxxxxxxx>
> ---
> drivers/tty/serial/8250/8250_dw.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index 977a473535e8..195aa4516b2b 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -755,7 +755,10 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = {
> .quirks = DW_UART_QUIRK_ARMADA_38X,
> };
>
> -static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {};
> +static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
...this change...
> + .quirks = DW_UART_QUIRK_IS_DMA_FC,
> + .cpr = 0x00012f32,
> +};
...and this will disappear from this patch.
With it rebased,
Reviewed-by: Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx>
> static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
> .quirks = DW_UART_QUIRK_SKIP_SET_RATE,
> --
> 2.27.0
>
--
With Best Regards,
Andy Shevchenko
