Dear Greg KH, I discussed with our silicon architect @Richard Petrie - M18281 and our answers are inline below. Please let us know if you need any further information. Thank You. Regards, Kumar > -----Original Message----- > From: Greg KH <gregkh@xxxxxxxxxxxxxxxxxxx> > Sent: Wednesday, February 9, 2022 5:01 PM > To: Kumaravel Thiagarajan - I21417 <Kumaravel.Thiagarajan@xxxxxxxxxxxxx> > Cc: linux-serial@xxxxxxxxxxxxxxx; Sundararaman Hariharaputran - I21286 > <Sundararaman.H@xxxxxxxxxxxxx>; Ronnie Kunin - C21729 > <Ronnie.Kunin@xxxxxxxxxxxxx>; Tharunkumar Pasumarthi - I67821 > <Tharunkumar.Pasumarthi@xxxxxxxxxxxxx>; Annirudh D - I64147 > <Annirudh.D@xxxxxxxxxxxxx>; Pragash Mangalapandian - I21326 > <Pragash.Mangalapandian@xxxxxxxxxxxxx> > Subject: Re: Reg: Serial port driver for microchip's new PCIe UART device > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > On Wed, Feb 09, 2022 at 10:38:34AM +0000, > Kumaravel.Thiagarajan@xxxxxxxxxxxxx wrote: > > Dear Greg KH, > > > > I am Kumaravel Thiagarajan from Microchip India. > > > > We are working on a PCIe based multi-instance UART device. > > Based on the Linux community feedback few months back, we had written > it as a custom driver inside drivers/tty/serial/8250. > > Now this custom driver is requiring a DWORD FIFO access for both Tx and > Rx, and I am in the process of changing my driver code. > > Why does the hardware not follow the normal standard here? We are building a PCIe 8250 based UART. We can absolutely support the normal 8250 framework and standard drivers. However, the challenges we see are the round-trip delays introduced by PCIe reads and writes having an impact on throughput, particularly if you are downstream of a PCIe tree with multiple hops. The sizes of the payloads are limited to 32-bit by the processor PIO, however, even going from 8-bit payloads to 32-bit payloads improves throughput dramatically. > > And are you sure it will still not fit into the 8250 format? As mentioned our hardware can support this, however, we see that it is less efficient due to the requirement for single byte reads and writes. > > > Can I model my custom driver on serial drivers present in drivers/tty/serial/ > directory? > > You could, but it would be much smaller and easier to use the 8250 > framework given that you probably do have an 8250-like device, right? Adding DWORD reads/writes to the hardware is a necessary enhancement for improved performance over PCIe. But 8250 framework looks very closely tied with reading character by character from the FIFO and I was not able to find a place in that framework where I could hook my own DWORD based Rx and Tx logic. Is there any DWORD based UART FIFO driver example with 8250 framework available? > > > I am implementing my functions for uart_ops structure and the necessary > ISR in a separate file mchp_pci1xxxx_uart.c inside the drivers/tty/serial/ > directory. > > > > I wish this custom UART driver to get through Linux community submission. > > Do you see any risk in this approach? Do you have any suggestions? > > Let's see the code before we can give you any firm answers. > > good luck! > > greg k-h
