Am 17.11.2021 um 06:16 schrieb Shubhrajyoti Datta:
"The uartlite is used by FPGAs that support a basically unlimited number of uarts so limiting it at 16 dosn't make sense as users might need more than that." the commit also said that number should be unlimited. However it set the default to 1 instead of 16.The original 16 written in driver should be quite reasonable default to cover most of the cases. So change the default number of uarts back to 16.
Respectfully, this is an inadequate fix to a decade-old underlying issue in the Xilinx device tree generator. The DTG assigns consecutive "port-number" properties to UARTs handled by separate drivers (uartps, uartlite, uartns), which are then used in drivers/tty/serial/uartlite.c to index the struct uart_port[] array and set uart_port->line. The DTG should number devices for each driver separately from 0; serial_core.c checks for (0 <= uart_port->line < NR_UART_PORTS). As a consequence, when a Zynq system has both a PS-UART and a Uartlite, setting SERIAL_UARTLITE_NR_UARTS explicitly to 1 in Kconfig means probing the uartlite fails, which is confusing to the unsuspecting KConfig user. Setting the default to 16 just kicks the can down the road because it will fail for more than 15 Uartlites (or less, if there are more PS-UARTs or AXI 16550A UARTs). I've submitted a patch for the DTG numbering scheme to git@xxxxxxxxxx just yesterday. Will post a PATCH to this list later today or tomorrow to handle the issue from the other end (uartlite.c). Cheers, Ruediger
