On Wed, May 17, 2017 at 8:43 AM, Dong Aisheng <dongas86@xxxxxxxxx> wrote:
> On Wed, May 17, 2017 at 08:37:41AM +0300, Nikita Yushchenko wrote:
>>
>>
>> 17.05.2017 06:39, Dong Aisheng wrote:
>> > On Tue, May 16, 2017 at 02:15:08PM +0300, Nikita Yushchenko wrote:
>> >>> static u32 lpuart32_read(void __iomem *addr)
>> >>> {
>> >>> - return ioread32be(addr);
>> >>> + return lpuart_is_be ? ioread32be(addr) : readl(addr);
>> >>> }
>> >>>
>> >>> static void lpuart32_write(u32 val, void __iomem *addr)
>> >>> {
>> >>> - iowrite32be(val, addr);
>> >>> + if (lpuart_is_be)
>> >>> + iowrite32be(val, addr);
>> >>> + else
>> >>> + writel(val, addr);
>> >>> }
>> >>
>> >> What if this is ever executed on big endian system?
>> >>
>> >
>> > Sorry, not catching the point...
>> >
>> > What issues will meet?
>>
>> Isn't writel() in host endian?
>
> On big endian systems, it is supposed to run iowrite32be.
It looks like you substituting *bus* side with CPU *side* of communication.
If you are talking about CPU side
__raw_readl() / __raw_writel() will do the trick.
--
With Best Regards,
Andy Shevchenko
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