On Tue, May 16, 2017 at 2:15 PM, Nikita Yushchenko
<nikita.yoush@xxxxxxxxxxxxxxxxxx> wrote:
>> static u32 lpuart32_read(void __iomem *addr)
>> {
>> - return ioread32be(addr);
>> + return lpuart_is_be ? ioread32be(addr) : readl(addr);
>> }
>>
>> static void lpuart32_write(u32 val, void __iomem *addr)
>> {
>> - iowrite32be(val, addr);
>> + if (lpuart_is_be)
>> + iowrite32be(val, addr);
>> + else
>> + writel(val, addr);
>> }
>
> What if this is ever executed on big endian system?
Above is apparently about bus side of communication and it looks like
it needs to be CPU side. Is this what you are trying to discuss?
--
With Best Regards,
Andy Shevchenko
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