On Fri, Jun 19, 2015 at 05:12:17PM +0200, Joerg Roedel wrote:
> From: Joerg Roedel <jroedel@xxxxxxx>
>
> While debugging why my 8-port XR17V35X card does not work
> with the in-kernel serial driver, I found that some chip
> specific wakeup code is necessary to get it working.
>
> Specificly the EFR_ECB bit needs to be set in the
> chip-specific UART_XR_EFR register, so that writing to a
> couple of other configuration bits is enabled.
>
> Cc: Peter Hurley <peter@xxxxxxxxxxxxxxxxxx>
> Cc: Michael Welling <mwelling@xxxxxxxx>
> Cc: Joe Schultz <jschultz@xxxxxxxxxxx>
> Signed-off-by: Joerg Roedel <jroedel@xxxxxxx>
> ---
> drivers/tty/serial/8250/8250_core.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
> index 4506e40..de34db3 100644
> --- a/drivers/tty/serial/8250/8250_core.c
> +++ b/drivers/tty/serial/8250/8250_core.c
> @@ -2176,6 +2176,18 @@ int serial8250_do_startup(struct uart_port *port)
> */
> enable_rsa(up);
> #endif
> +
> + /*
> + * Do this right before clearing the FIFOs to prevent
> + * interrupt storm.
> + */
> + if (port->type == PORT_XR17V35X) {
> + /* Wake up and initialize UART */
> + serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
> + serial_port_out(port, UART_IER, 0);
> + serial_port_out(port, UART_LCR, 0);
> + }
> +
Looks good to me. The datasheet indicates that bit 4 of the EFR needs to be set to access
to IER [7:5], ISR [5:4], FCR[5:4], MCR[7:5], MSR.
> /*
> * Clear the FIFO buffers and disable them.
> * (they will be reenabled in set_termios())
> --
> 1.8.4.5
>
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