On 05/05/2014 05:03 PM, Peter Korsgaard wrote: >>>>>> "Michal" == Michal Simek <michal.simek@xxxxxxxxxx> writes: > > > Xilinx MDM (Microblaze Debug Module) also contains > > uart interface via JTAG which is compatible with > > uartlite driver. This interface is really slow > > that's why timeout is setup to 1s. > > > Make this time delay not to be cpu speed dependent. > > > Signed-off-by: Michal Simek <michal.simek@xxxxxxxxxx> > > --- > > > RFC sent here: > > https://lkml.org/lkml/2013/9/30/250 > > I finally got HW design which is just slow to be able > > to test it. > > > --- > > drivers/tty/serial/uartlite.c | 10 ++++++++-- > > 1 file changed, 8 insertions(+), 2 deletions(-) > > > diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c > > index 5f90ef24d475..723a6b79cd14 100644 > > --- a/drivers/tty/serial/uartlite.c > > +++ b/drivers/tty/serial/uartlite.c > > @@ -418,14 +418,20 @@ static struct uart_ops ulite_ops = { > > #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE > > static void ulite_console_wait_tx(struct uart_port *port) > > { > > - int i; > > u8 val; > > + unsigned long timeout; > > > /* Spin waiting for TX fifo to have space available */ > > - for (i = 0; i < 100000; i++) { > > It would be good to add a note about the slow jtag variant here. What exactly you would like to see here? Just that this 1s is here because of mdm uart. You can find out commit ID via git blame and description is in commit message. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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