Xilinx MDM (Microblaze Debug Module) also contains uart interface via JTAG which is compatible with uartlite driver. This interface is really slow that's why timeout is setup to 1s. Make this time delay not to be cpu speed dependent. Signed-off-by: Michal Simek <michal.simek@xxxxxxxxxx> --- RFC sent here: https://lkml.org/lkml/2013/9/30/250 I finally got HW design which is just slow to be able to test it. --- drivers/tty/serial/uartlite.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/uartlite.c b/drivers/tty/serial/uartlite.c index 5f90ef24d475..723a6b79cd14 100644 --- a/drivers/tty/serial/uartlite.c +++ b/drivers/tty/serial/uartlite.c @@ -418,14 +418,20 @@ static struct uart_ops ulite_ops = { #ifdef CONFIG_SERIAL_UARTLITE_CONSOLE static void ulite_console_wait_tx(struct uart_port *port) { - int i; u8 val; + unsigned long timeout; /* Spin waiting for TX fifo to have space available */ - for (i = 0; i < 100000; i++) { + timeout = jiffies + msecs_to_jiffies(1000); + while (1) { val = uart_in32(ULITE_STATUS, port); if ((val & ULITE_STATUS_TXFULL) == 0) break; + if (time_after(jiffies, timeout)) { + dev_warn(port->dev, + "timeout waiting for TX buffer empty\n"); + break; + } cpu_relax(); } } -- 1.8.2.3
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