Stephen Warren <swarren@xxxxxxxxxxxxx> : >> All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011 >> TRM: >> >> r1p4-r1p5 Contains the following differences in functionality: >> * The receive and transmit FIFOs are increased to a depth of 32. >> * The Revision field in the UARTPeriphID2 Register on page 3-24 >> bits [7:4] now reads back as 0x3. > > Well, that certainly isn't true in practice. I think we should revert > this commit until we can determine what the problem is. I asked to the ARM support about this. Waiting for reply.. -- To unsubscribe from this list: send the line "unsubscribe linux-serial" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
