Hi. We noticed that we were loosing data at speed less than 2400 baud. It turned out our (TI16750 compatible) uart with 64 byte outgoing fifo was truncated to 16 byte (bit 5 sets fifo len) when modifying the fcr reg. The input code still fills the buffer with 64 bytes if I remember correctly and thus data is lost. Our fix was to remove whiping of the fcr content and just add the TRIGGER_1 which we want for latency. I can't see why this would not work on less than 2400 always, for all uarts... Otherwise one would have to make sure the filling of the fifo re-checks the current state of available fifo size (urrk). Best regards, Christian Melki
Attachment:
8250-fix.patch
Description: 8250-fix.patch
