RE: [PATCH 2/2] scsi: pm80xx: enable upper inbound, outbound queues

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Thanks Damien for your comments here. Will make these changes in
PATCH V2.

> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
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> 
> On 3/28/22 17:42, Ajish Koshy wrote:
> > Executing driver on servers with more than 32 CPUs were faced with
> > command timeouts. This is because we were not geting completions for
> > commands submitted on IQ32 - IQ63.
> >
> > Set E64Q bit to enable upper inbound and outbound queues 32 to 63 in
> > the MPI main configuration table.
> >
> > Added 500ms delay after successful MPI initialization as mentioned in
> > controller datasheet.
> >
> > Signed-off-by: Ajish Koshy <Ajish.Koshy@xxxxxxxxxxxxx>
> > Signed-off-by: Viswas G <Viswas.G@xxxxxxxxxxxxx>
> > ---
> >  drivers/scsi/pm8001/pm80xx_hwi.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c
> > b/drivers/scsi/pm8001/pm80xx_hwi.c
> > index b92e82a576e3..f04c6c589615 100644
> > --- a/drivers/scsi/pm8001/pm80xx_hwi.c
> > +++ b/drivers/scsi/pm8001/pm80xx_hwi.c
> > @@ -766,6 +766,10 @@ static void init_default_table_values(struct
> pm8001_hba_info *pm8001_ha)
> >       pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity       =
> 0x01;
> >       pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt          = 0x01;
> >
> > +     /* Enable higher IQs and OQs, 32 to 63, bit 16*/
> > +     if (pm8001_ha->max_q_num > 32)
> > +             pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
> > +                                                     (1 << 16);
> 
> No need for the brackets.

OK
> 
> >       /* Disable end to end CRC checking */
> >       pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
> >
> > @@ -1027,6 +1031,9 @@ static int mpi_init_check(struct
> pm8001_hba_info *pm8001_ha)
> >       if (0x0000 != gst_len_mpistate)
> >               return -EBUSY;
> >
> > +     /* Wait for 500ms after successful MPI initialization*/
> 
> Is this comment really necessary ? Anybody sees that this will wait. It may be
> better to explain *why* the wait is needed.

Yes you may be right here. The code itself speaks about this. 

The reason for delay is not mentioned in the datasheet.

When going through this E64Q bit details they mentioned about the MPI
initialization steps to be followed. 
Since MPI Initialization is mentioned separately irrespective of E64Q bit, I believe
this may be needed to be followed in all the cases.

Well here controller datasheet is not talking much on this wait. It simply says
"Note: It is recommended to wait 500ms after the MPI-S field indicates
the host has successfully initialized the MPI before sending commands."

> 
> > +     msleep(500);
> > +
> >       return 0;
> >  }
> >
> 
> 
> --
> Damien Le Moal
> Western Digital Research

Thanks,
Ajish




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