On 19/12/2018 18:27, Marc Gonzalez wrote:
> On 18/12/2018 17:54, Marc Gonzalez wrote:
>
>> Now the fun begins, to find the tiny difference that makes/breaks everything :-)
> I thought I had found the problem:
> "clk_set_rate: ufs_unipro_core_clk_src" was not occurring.
> But, in fact, I think the bootloader already set the proper rate.
Found something fishy...
Downstream, the PHY clocks are:
<&clock_gcc clk_ln_bb_clk1>, // ???
<&clock_gcc clk_gcc_ufs_clkref_clk>, // 0x88004
<&clock_gcc clk_gcc_ufs_phy_aux_hw_ctl_clk>; // 0x76040
If I examine these clocks in debugfs:
# for F in ln_bb_clk1/* gcc_ufs_clkref_clk/* gcc_ufs_phy_aux_*/*; do echo $F; cat $F; done
ln_bb_clk1/enable
0
ln_bb_clk1/has_hw_gating
0
ln_bb_clk1/is_local
0
ln_bb_clk1/parent
None
ln_bb_clk1/print
ln_bb_clk1
ln_bb_clk1/rate
1000
gcc_ufs_clkref_clk/enable
0
gcc_ufs_clkref_clk/has_hw_gating
0
gcc_ufs_clkref_clk/is_local
1
gcc_ufs_clkref_clk/list_rates
gcc_ufs_clkref_clk/parent
None
gcc_ufs_clkref_clk/print
gcc_ufs_clkref_clk
CBCR: 0x80000000
gcc_ufs_clkref_clk/rate
0
gcc_ufs_phy_aux_clk/enable
0
gcc_ufs_phy_aux_clk/has_hw_gating
0
gcc_ufs_phy_aux_clk/is_local
1
gcc_ufs_phy_aux_clk/list_rates
19200000
gcc_ufs_phy_aux_clk/parent
ufs_phy_aux_clk_src
gcc_ufs_phy_aux_clk/print
cxo_clk_src
ufs_phy_aux_clk_src
CMD_RCGR: 0x80000000
CFG_RCGR: 0x00000000
gcc_ufs_phy_aux_clk
CBCR: 0x80000000
gcc_ufs_phy_aux_clk/rate
19200000
gcc_ufs_phy_aux_hw_ctl_clk/enable
0
gcc_ufs_phy_aux_hw_ctl_clk/has_hw_gating
0
gcc_ufs_phy_aux_hw_ctl_clk/is_local
1
gcc_ufs_phy_aux_hw_ctl_clk/parent
gcc_ufs_phy_aux_clk
gcc_ufs_phy_aux_hw_ctl_clk/print
cxo_clk_src
ufs_phy_aux_clk_src
CMD_RCGR: 0x80000000
CFG_RCGR: 0x00000000
gcc_ufs_phy_aux_clk
CBCR: 0x80000000
gcc_ufs_phy_aux_hw_ctl_clk
gcc_ufs_phy_aux_hw_ctl_clk/rate
19200000
The gcc_ufs_phy_aux_clk ticks at 19.2 Mhz
Compare this with upstream:
<&gcc GCC_UFS_CLKREF_CLK>, // 0x88004
<&gcc GCC_UFS_PHY_AUX_CLK>; // 0x76040
(I provided only two clocks because the bindings doc says
For "qcom,sdm845-qmp-ufs-phy" must contain:
"ref", "ref_aux".
Jeffrey: does that look good to you? I'm using the sdm845 PHY BTW)
# for F in ln_bb_clk1/* gcc_ufs_clkref_clk/* gcc_ufs_phy_aux_*/*; do echo $F; cat $F; done
ln_bb_clk1/clk_accuracy
0
ln_bb_clk1/clk_duty_cycle
1/2
ln_bb_clk1/clk_enable_count
0
ln_bb_clk1/clk_flags
ln_bb_clk1/clk_notifier_count
0
ln_bb_clk1/clk_phase
0
ln_bb_clk1/clk_prepare_count
0
ln_bb_clk1/clk_protect_count
0
ln_bb_clk1/clk_rate
19200000
gcc_ufs_clkref_clk/clk_accuracy
0
gcc_ufs_clkref_clk/clk_duty_cycle
1/2
gcc_ufs_clkref_clk/clk_enable_count
0
gcc_ufs_clkref_clk/clk_flags
gcc_ufs_clkref_clk/clk_notifier_count
0
gcc_ufs_clkref_clk/clk_phase
0
gcc_ufs_clkref_clk/clk_prepare_count
0
gcc_ufs_clkref_clk/clk_protect_count
0
gcc_ufs_clkref_clk/clk_rate
19200000
gcc_ufs_phy_aux_clk/clk_accuracy
0
gcc_ufs_phy_aux_clk/clk_duty_cycle
1/2
gcc_ufs_phy_aux_clk/clk_enable_count
0
gcc_ufs_phy_aux_clk/clk_flags
gcc_ufs_phy_aux_clk/clk_notifier_count
0
gcc_ufs_phy_aux_clk/clk_phase
0
gcc_ufs_phy_aux_clk/clk_prepare_count
0
gcc_ufs_phy_aux_clk/clk_protect_count
0
gcc_ufs_phy_aux_clk/clk_rate
0
The gcc_ufs_phy_aux_clk rate is 0. That might be important...
