On 18/12/2018 17:54, Marc Gonzalez wrote: > Now the fun begins, to find the tiny difference that makes/breaks everything :-) I thought I had found the problem: "clk_set_rate: ufs_unipro_core_clk_src" was not occurring. But, in fact, I think the bootloader already set the proper rate. I'll have to take another look tomorrow... Regards. [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x51af8014] [ 0.000000] Linux version 4.20.0-rc4 (mgonzalez@venus) (gcc version 7.3.1 20180425 [linaro-7.3-2018.05 revision d29120a424ecfbc167ef90065c0eeb7f91977701] (Linaro GCC 7.3-2018.05)) #4 SMP PREEMPT Wed Dec 19 18:19:29 CET 2018 [ 0.000000] Machine model: Qualcomm Technologies, Inc. MSM8998 v1 MTP [ 0.000000] printk: debug: ignoring loglevel setting. [ 0.000000] On node 0 totalpages: 1028544 [ 0.000000] DMA32 zone: 8192 pages used for memmap [ 0.000000] DMA32 zone: 0 pages reserved [ 0.000000] DMA32 zone: 511488 pages, LIFO batch:63 [ 0.000000] Normal zone: 8079 pages used for memmap [ 0.000000] Normal zone: 517056 pages, LIFO batch:63 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.0 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.0 [ 0.000000] random: get_random_bytes called from start_kernel+0xb0/0x44c with crng_init=0 [ 0.000000] percpu: Embedded 22 pages/cpu @(____ptrval____) s49816 r8192 d32104 u90112 [ 0.000000] pcpu-alloc: s49816 r8192 d32104 u90112 alloc=22*4096 [ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 [0] 7 [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI) [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1012273 [ 0.000000] Kernel command line: console=ttyMSM0,115200,n8 ignore_loglevel trace_event=ufs:*,scsi:*,clk:*,regulator:* tp_printk nosmp clk_ignore_unused androidboot.bootdevice=1da4000.ufshc androidboot.serialno=53733c35 androidboot.baseband=apq mdss_mdp.panel=1:hdmi:16 [ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes) [ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes) [ 0.000000] software IO TLB: mapped [mem 0xfbfff000-0xfffff000] (64MB) [ 0.000000] Memory: 3962916K/4114176K available (3390K kernel code, 390K rwdata, 1012K rodata, 7232K init, 234K bss, 151260K reserved, 0K cma-reserved) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1 [ 0.000000] ftrace: allocating 13117 entries in 52 pages [ 0.000000] rcu: Preemptible hierarchical RCU implementation. [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=8. [ 0.000000] Tasks RCU enabled. [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 [ 0.000000] GICv3: Distributor has no Range Selector support [ 0.000000] GICv3: no VLPI support, no direct LPI support [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x0000000017b00000 [ 0.000000] ITS: No ITS available, not enabling LPIs [ 0.000000] arch_timer: cp15 and mmio timer(s) running at 19.20MHz (virt/virt). [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x46d987e47, max_idle_ns: 440795202767 ns [ 0.000003] sched_clock: 56 bits at 19MHz, resolution 52ns, wraps every 4398046511078ns [ 0.000062] Console: colour dummy device 80x25 [ 0.000082] Calibrating delay loop (skipped), value calculated using timer frequency.. 38.40 BogoMIPS (lpj=76800) [ 0.000090] pid_max: default: 32768 minimum: 301 [ 0.000184] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes) [ 0.000199] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes) [ 0.023911] ASID allocator initialised with 32768 entries [ 0.031909] rcu: Hierarchical SRCU implementation. [ 0.047939] smp: Bringing up secondary CPUs ... [ 0.047946] smp: Brought up 1 node, 1 CPU [ 0.047951] SMP: Total of 1 processors activated. [ 0.047960] CPU features: detected: GIC system register CPU interface [ 0.047967] CPU features: detected: 32-bit EL0 Support [ 0.047973] CPU features: detected: CRC32 instructions [ 0.051379] CPU: All CPU(s) started at EL1 [ 0.051391] alternatives: patching kernel code [ 0.051945] devtmpfs: initialized [ 0.054833] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns [ 0.054845] futex hash table entries: 2048 (order: 5, 131072 bytes) [ 0.054954] pinctrl core: initialized pinctrl subsystem [ 0.055204] regulator_enable: name=regulator-dummy [ 0.055748] vdso: 2 pages (1 code @ (____ptrval____), 1 data @ (____ptrval____)) [ 0.055829] DMA: preallocated 256 KiB pool for atomic allocations [ 0.058235] clk_prepare: gcc_hmss_dvm_bus_clk [ 0.058243] clk_prepare_complete: gcc_hmss_dvm_bus_clk [ 0.058252] clk_enable: gcc_hmss_dvm_bus_clk [ 0.058264] clk_enable_complete: gcc_hmss_dvm_bus_clk [ 0.058358] clk_prepare: gcc_lpass_at_clk [ 0.058364] clk_prepare_complete: gcc_lpass_at_clk [ 0.058371] clk_enable: gcc_lpass_at_clk [ 0.058380] clk_enable_complete: gcc_lpass_at_clk [ 0.058416] clk_prepare: gcc_mmss_noc_cfg_ahb_clk [ 0.058423] clk_prepare_complete: gcc_mmss_noc_cfg_ahb_clk [ 0.058429] clk_enable: gcc_mmss_noc_cfg_ahb_clk [ 0.058439] clk_enable_complete: gcc_mmss_noc_cfg_ahb_clk [ 0.084356] regulator_enable: name=vph_pwr [ 0.084812] SCSI subsystem initialized [ 0.088197] clocksource: Switched to clocksource arch_sys_counter [ 0.100307] s1: supplied by vph_pwr [ 0.100874] s2: supplied by vph_pwr [ 0.101244] s3: supplied by vph_pwr [ 0.101311] s3: Bringing 0uV into 1352000-1352000uV [ 0.101397] regulator_set_voltage: name=s3 (1352000-1352000) [ 0.104268] regulator_set_voltage_complete: name=s3, val=320000 [ 0.104542] s4: supplied by vph_pwr [ 0.104674] s4: Bringing 0uV into 1800000-1800000uV [ 0.104682] regulator_set_voltage: name=s4 (1800000-1800000) [ 0.105174] regulator_set_voltage_complete: name=s4, val=320000 [ 0.105377] s5: supplied by vph_pwr [ 0.105424] s5: Bringing 0uV into 1904000-1904000uV [ 0.105433] regulator_set_voltage: name=s5 (1904000-1904000) [ 0.105626] regulator_set_voltage_complete: name=s5, val=320000 [ 0.105867] s6: supplied by vph_pwr [ 0.106118] s7: supplied by vph_pwr [ 0.106167] s7: Bringing 0uV into 900000-900000uV [ 0.106176] regulator_set_voltage: name=s7 (900000-900000) [ 0.106289] regulator_set_voltage_complete: name=s7, val=320000 [ 0.106599] s8: supplied by vph_pwr [ 0.106866] s9: supplied by vph_pwr [ 0.107144] s10: supplied by vph_pwr [ 0.107429] s11: supplied by vph_pwr [ 0.107760] s12: supplied by vph_pwr [ 0.108152] s13: supplied by vph_pwr [ 0.108451] l1: supplied by s7 [ 0.108572] l1: Bringing 0uV into 880000-880000uV [ 0.108581] regulator_set_voltage: name=l1 (880000-880000) [ 0.112252] regulator_set_voltage_complete: name=l1, val=312000 [ 0.112515] l2: supplied by s3 [ 0.112568] l2: Bringing 0uV into 1200000-1200000uV [ 0.112578] regulator_set_voltage: name=l2 (1200000-1200000) [ 0.112676] regulator_set_voltage_complete: name=l2, val=312000 [ 0.112898] l3: supplied by s7 [ 0.112953] l3: Bringing 0uV into 1000000-1000000uV [ 0.112961] regulator_set_voltage: name=l3 (1000000-1000000) [ 0.113064] regulator_set_voltage_complete: name=l3, val=312000 [ 0.113296] l4: supplied by s7 [ 0.113650] l5: supplied by s7 [ 0.113703] l5: Bringing 0uV into 800000-800000uV [ 0.113710] regulator_set_voltage: name=l5 (800000-800000) [ 0.113823] regulator_set_voltage_complete: name=l5, val=312000 [ 0.114047] l6: supplied by s5 [ 0.114099] l6: Bringing 0uV into 1808000-1808000uV [ 0.114108] regulator_set_voltage: name=l6 (1808000-1808000) [ 0.114213] regulator_set_voltage_complete: name=l6, val=1664000 [ 0.114445] l7: supplied by s5 [ 0.114500] l7: Bringing 0uV into 1800000-1800000uV [ 0.114509] regulator_set_voltage: name=l7 (1800000-1800000) [ 0.114618] regulator_set_voltage_complete: name=l7, val=1256000 [ 0.114835] l8: supplied by s3 [ 0.114965] l8: Bringing 0uV into 1200000-1200000uV [ 0.114975] regulator_set_voltage: name=l8 (1200000-1200000) [ 0.116328] regulator_set_voltage_complete: name=l8, val=312000 [ 0.116564] l9: Bringing 0uV into 1808000-1808000uV [ 0.116572] regulator_set_voltage: name=l9 (1808000-1808000) [ 0.116683] regulator_set_voltage_complete: name=l9, val=1664000 [ 0.116915] l10: Bringing 0uV into 1808000-1808000uV [ 0.116924] regulator_set_voltage: name=l10 (1808000-1808000) [ 0.117029] regulator_set_voltage_complete: name=l10, val=1664000 [ 0.117280] l11: supplied by s7 [ 0.117330] l11: Bringing 0uV into 1000000-1000000uV [ 0.117337] regulator_set_voltage: name=l11 (1000000-1000000) [ 0.117437] regulator_set_voltage_complete: name=l11, val=312000 [ 0.117680] l12: supplied by s5 [ 0.117727] l12: Bringing 0uV into 1800000-1800000uV [ 0.117738] regulator_set_voltage: name=l12 (1800000-1800000) [ 0.117814] regulator_set_voltage_complete: name=l12, val=1256000 [ 0.118134] l13: Bringing 0uV into 1808000-1808000uV [ 0.118143] regulator_set_voltage: name=l13 (1808000-1808000) [ 0.120258] regulator_set_voltage_complete: name=l13, val=1664000 [ 0.120524] l14: supplied by s5 [ 0.120578] l14: Bringing 0uV into 1880000-1880000uV [ 0.120589] regulator_set_voltage: name=l14 (1880000-1880000) [ 0.120693] regulator_set_voltage_complete: name=l14, val=1256000 [ 0.120963] l15: supplied by s5 [ 0.121011] l15: Bringing 0uV into 1800000-1800000uV [ 0.121020] regulator_set_voltage: name=l15 (1800000-1800000) [ 0.121121] regulator_set_voltage_complete: name=l15, val=1256000 [ 0.121400] l16: Bringing 0uV into 2704000-2704000uV [ 0.121409] regulator_set_voltage: name=l16 (2704000-2704000) [ 0.121518] regulator_set_voltage_complete: name=l16, val=1664000 [ 0.121785] l17: supplied by s3 [ 0.121905] l17: Bringing 0uV into 1304000-1304000uV [ 0.121914] regulator_set_voltage: name=l17 (1304000-1304000) [ 0.122025] regulator_set_voltage_complete: name=l17, val=312000 [ 0.122353] l18: Bringing 0uV into 2704000-2704000uV [ 0.122363] regulator_set_voltage: name=l18 (2704000-2704000) [ 0.122464] regulator_set_voltage_complete: name=l18, val=1664000 [ 0.122759] l19: Bringing 0uV into 3008000-3008000uV [ 0.122770] regulator_set_voltage: name=l19 (3008000-3008000) [ 0.124234] regulator_set_voltage_complete: name=l19, val=1664000 [ 0.124548] l20: Bringing 0uV into 2960000-2960000uV [ 0.124557] regulator_set_voltage: name=l20 (2960000-2960000) [ 0.124670] regulator_set_voltage_complete: name=l20, val=1664000 [ 0.125001] l21: Bringing 0uV into 2960000-2960000uV [ 0.125010] regulator_set_voltage: name=l21 (2960000-2960000) [ 0.125126] regulator_set_voltage_complete: name=l21, val=1664000 [ 0.125485] l22: Bringing 0uV into 2864000-2864000uV [ 0.125494] regulator_set_voltage: name=l22 (2864000-2864000) [ 0.125596] regulator_set_voltage_complete: name=l22, val=1664000 [ 0.125973] l23: Bringing 0uV into 3312000-3312000uV [ 0.125983] regulator_set_voltage: name=l23 (3312000-3312000) [ 0.126086] regulator_set_voltage_complete: name=l23, val=1664000 [ 0.126570] l24: Bringing 0uV into 3088000-3088000uV [ 0.126581] regulator_set_voltage: name=l24 (3088000-3088000) [ 0.128243] regulator_set_voltage_complete: name=l24, val=1664000 [ 0.128649] l25: Bringing 0uV into 3104000-3104000uV [ 0.128656] regulator_set_voltage: name=l25 (3104000-3104000) [ 0.128771] regulator_set_voltage_complete: name=l25, val=1664000 [ 0.129203] l26: supplied by s3 [ 0.129259] l26: Bringing 0uV into 1200000-1200000uV [ 0.129268] regulator_set_voltage: name=l26 (1200000-1200000) [ 0.129402] regulator_set_voltage_complete: name=l26, val=312000 [ 0.129809] l27: supplied by s7 [ 0.130283] l28: Bringing 0uV into 3008000-3008000uV [ 0.130292] regulator_set_voltage: name=l28 (3008000-3008000) [ 0.131813] regulator_set_voltage_complete: name=l28, val=1664000 [ 0.132336] lvs1: supplied by s4 [ 0.132933] lvs2: supplied by s4 [ 0.134307] bob: supplied by vph_pwr [ 0.134374] bob: Bringing 0uV into 3312000-3312000uV [ 0.134383] regulator_set_voltage: name=bob (3312000-3312000) [ 0.135452] regulator_set_voltage_complete: name=bob, val=3312000 [ 0.471726] workingset: timestamp_bits=62 max_order=20 bucket_order=0 [ 0.483568] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 253) [ 0.483621] io scheduler noop registered (default) [ 0.485942] qcom-qmp-phy 1da7000.phy: Linked as a consumer to regulator.15 [ 0.486051] qcom-qmp-phy 1da7000.phy: Linked as a consumer to regulator.16 [ 0.487497] qcom-qmp-phy 1da7000.phy: Registered Qcom-QMP phy [ 0.498172] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 0.504436] msm_serial c1b0000.serial: msm_serial: detected port #0 [ 0.504540] msm_serial c1b0000.serial: uartclk = 1843200 [ 0.504708] c1b0000.serial: ttyMSM0 at MMIO 0xc1b0000 (irq = 13, base_baud = 115200) is a MSM [ 0.504812] clk_prepare: xo_board [ 0.504849] clk_prepare_complete: xo_board [ 0.504859] clk_prepare: xo [ 0.504866] clk_prepare_complete: xo [ 0.504879] clk_prepare: blsp2_uart2_apps_clk_src [ 0.504887] clk_prepare_complete: blsp2_uart2_apps_clk_src [ 0.504896] clk_prepare: gcc_blsp2_uart2_apps_clk [ 0.504906] clk_prepare_complete: gcc_blsp2_uart2_apps_clk [ 0.504938] clk_enable: xo_board [ 0.504958] clk_enable_complete: xo_board [ 0.504966] clk_enable: xo [ 0.504973] clk_enable_complete: xo [ 0.504983] clk_enable: blsp2_uart2_apps_clk_src [ 0.504995] clk_enable_complete: blsp2_uart2_apps_clk_src [ 0.505003] clk_enable: gcc_blsp2_uart2_apps_clk [ 0.505048] clk_enable_complete: gcc_blsp2_uart2_apps_clk [ 0.505062] clk_prepare: gcc_blsp2_ahb_clk [ 0.505071] clk_prepare_complete: gcc_blsp2_ahb_clk [ 0.505082] clk_enable: gcc_blsp2_ahb_clk [ 0.505097] clk_enable_complete: gcc_blsp2_ahb_clk [ 0.505142] msm_serial: console setup on port #0 [ 0.505468] clk_prepare: gpll0 [ 0.505476] clk_prepare_complete: gpll0 [ 0.505484] clk_prepare: gpll0_out_main [ 0.505493] clk_prepare_complete: gpll0_out_main [ 0.505502] clk_enable: gpll0 [ 0.505531] clk_enable_complete: gpll0 [ 0.505537] clk_enable: gpll0_out_main [ 0.505546] clk_enable_complete: gpll0_out_main [ 0.505582] clk_set_parent: blsp2_uart2_apps_clk_src gpll0_out_main [ 0.505644] clk_set_parent_complete: blsp2_uart2_apps_clk_src gpll0_out_main [ 0.505671] clk_set_rate: blsp2_uart2_apps_clk_src 3686400 [ 0.505692] clk_set_rate_complete: blsp2_uart2_apps_clk_src 3686400 [ 0.505711] clk_set_rate: gcc_blsp2_uart2_apps_clk 3686400 [ 0.505721] clk_set_rate_complete: gcc_blsp2_uart2_apps_clk 3686400 [ 1.819345] printk: console [ttyMSM0] enabled [ 1.826517] msm_serial: driver initialized [ 1.836524] ufshcd-qcom 1da4000.ufshc: freq-table-hz: min 50000000 max 200000000 name core_clk [ 1.836605] ufshcd-qcom 1da4000.ufshc: freq-table-hz: min 0 max 0 name bus_aggr_clk [ 1.844155] ufshcd-qcom 1da4000.ufshc: freq-table-hz: min 0 max 0 name iface_clk [ 1.851674] ufshcd-qcom 1da4000.ufshc: freq-table-hz: min 37500000 max 150000000 name core_clk_unipro [ 1.859303] ufshcd-qcom 1da4000.ufshc: freq-table-hz: min 75000000 max 300000000 name core_clk_ice [ 1.868413] ufshcd-qcom 1da4000.ufshc: freq-table-hz: min 0 max 0 name ref_clk [ 1.877243] ufshcd-qcom 1da4000.ufshc: freq-table-hz: min 0 max 0 name tx_lane0_sync_clk [ 1.884450] ufshcd-qcom 1da4000.ufshc: freq-table-hz: min 0 max 0 name rx_lane0_sync_clk [ 1.892697] ufshcd-qcom 1da4000.ufshc: freq-table-hz: min 0 max 0 name rx_lane1_sync_clk [ 1.900789] ufshcd-qcom 1da4000.ufshc: ufshcd_populate_vreg: Unable to find vdd-hba-supply regulator, assuming enabled [ 1.909207] clk_set_rate: ufs_axi_clk_src 200000000 [ 1.919365] clk_set_rate_complete: ufs_axi_clk_src 200000000 [ 1.924108] clk_set_rate: gcc_aggre1_ufs_axi_clk 200000000 [ 1.930004] clk_set_rate_complete: gcc_aggre1_ufs_axi_clk 200000000 [ 1.935304] clk_set_rate: gcc_ufs_axi_clk 200000000 [ 1.941458] clk_set_rate_complete: gcc_ufs_axi_clk 200000000 [ 1.946328] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk, rate: 198400000 [ 1.952254] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: bus_aggr_clk, rate: 198400000 [ 1.960327] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: iface_clk, rate: 0 [ 1.968858] clk_set_rate: ufs_unipro_core_clk_src 150000000 [ 1.976279] clk_set_rate_complete: ufs_unipro_core_clk_src 150000000 [ 1.981747] clk_set_rate: gcc_ufs_unipro_core_clk 150000000 [ 1.988339] clk_set_rate_complete: gcc_ufs_unipro_core_clk 150000000 [ 1.993638] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_unipro, rate: 148800000 [ 2.000267] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: core_clk_ice, rate: 0 [ 2.009034] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: ref_clk, rate: 19200000 [ 2.016750] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: tx_lane0_sync_clk, rate: 0 [ 2.024571] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: rx_lane0_sync_clk, rate: 0 [ 2.032898] ufshcd-qcom 1da4000.ufshc: ufshcd_init_clocks: clk: rx_lane1_sync_clk, rate: 0 [ 2.041139] clk_prepare: ufs_axi_clk_src [ 2.049352] clk_prepare_complete: ufs_axi_clk_src [ 2.053435] clk_prepare: gcc_ufs_axi_clk [ 2.058032] clk_prepare_complete: gcc_ufs_axi_clk [ 2.062035] clk_enable: ufs_axi_clk_src [ 2.066633] clk_enable_complete: ufs_axi_clk_src [ 2.070265] clk_enable: gcc_ufs_axi_clk [ 2.075129] clk_enable_complete: gcc_ufs_axi_clk [ 2.078702] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk enabled [ 2.083580] clk_prepare: gcc_aggre1_ufs_axi_clk [ 2.090931] clk_prepare_complete: gcc_aggre1_ufs_axi_clk [ 2.095453] clk_enable: gcc_aggre1_ufs_axi_clk [ 2.101001] clk_enable_complete: gcc_aggre1_ufs_axi_clk [ 2.105260] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: bus_aggr_clk enabled [ 2.110401] clk_prepare: gcc_ufs_ahb_clk [ 2.118358] clk_prepare_complete: gcc_ufs_ahb_clk [ 2.122530] clk_enable: gcc_ufs_ahb_clk [ 2.127124] clk_enable_complete: gcc_ufs_ahb_clk [ 2.130779] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: iface_clk enabled [ 2.135662] clk_prepare: ufs_unipro_core_clk_src [ 2.143363] clk_prepare_complete: ufs_unipro_core_clk_src [ 2.147970] clk_prepare: gcc_ufs_unipro_core_clk [ 2.153259] clk_prepare_complete: gcc_ufs_unipro_core_clk [ 2.157954] clk_enable: ufs_unipro_core_clk_src [ 2.163231] clk_enable_complete: ufs_unipro_core_clk_src [ 2.167583] clk_enable: gcc_ufs_unipro_core_clk [ 2.173132] clk_enable_complete: gcc_ufs_unipro_core_clk [ 2.177400] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk_unipro enabled [ 2.182973] clk_prepare: gcc_ufs_ice_core_clk [ 2.191020] clk_prepare_complete: gcc_ufs_ice_core_clk [ 2.195453] clk_enable: gcc_ufs_ice_core_clk [ 2.200474] clk_enable_complete: gcc_ufs_ice_core_clk [ 2.204912] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk_ice enabled [ 2.209885] clk_prepare: ln_bb_clk1 [ 2.217989] clk_prepare_complete: ln_bb_clk1 [ 2.221142] clk_enable: ln_bb_clk1 [ 2.225640] clk_enable_complete: ln_bb_clk1 [ 2.228865] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: ref_clk enabled [ 2.232970] clk_prepare: gcc_ufs_tx_symbol_0_clk [ 2.240586] clk_prepare_complete: gcc_ufs_tx_symbol_0_clk [ 2.245367] clk_enable: gcc_ufs_tx_symbol_0_clk [ 2.250648] clk_enable_complete: gcc_ufs_tx_symbol_0_clk [ 2.255002] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: tx_lane0_sync_clk enabled [ 2.260583] clk_prepare: gcc_ufs_rx_symbol_0_clk [ 2.268971] clk_prepare_complete: gcc_ufs_rx_symbol_0_clk [ 2.273577] clk_enable: gcc_ufs_rx_symbol_0_clk [ 2.278860] clk_enable_complete: gcc_ufs_rx_symbol_0_clk [ 2.283214] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: rx_lane0_sync_clk enabled [ 2.288793] clk_prepare: gcc_ufs_rx_symbol_1_clk [ 2.297184] clk_prepare_complete: gcc_ufs_rx_symbol_1_clk [ 2.301791] clk_enable: gcc_ufs_rx_symbol_1_clk [ 2.307071] clk_enable_complete: gcc_ufs_rx_symbol_1_clk [ 2.311425] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: rx_lane1_sync_clk enabled [ 2.317038] ufshcd_clk_gating: 1da4000.ufshc: gating state changed to CLKS_ON [ 2.325441] ufshcd_profile_clk_gating: 1da4000.ufshc: on: took 284283 usecs, err 0 [ 2.332659] l20: supplied by bob [ 2.340164] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.34 [ 2.343410] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.40 [ 2.350076] ufshcd-qcom 1da4000.ufshc: Linked as a consumer to regulator.5 [ 2.356991] regulator_enable: name=bob [ 2.363935] regulator_enable_delay: name=bob [ 2.367595] regulator_enable_complete: name=bob [ 2.372008] regulator_enable: name=l20 [ 2.376697] regulator_enable_delay: name=l20 [ 2.380076] regulator_enable_complete: name=l20 [ 2.384530] regulator_enable: name=s3 [ 2.388828] regulator_enable_delay: name=s3 [ 2.392579] regulator_enable_complete: name=s3 [ 2.396576] regulator_enable: name=l26 [ 2.401333] regulator_enable_delay: name=l26 [ 2.404823] regulator_enable_complete: name=l26 [ 2.409253] regulator_enable: name=s4 [ 2.413564] regulator_enable_delay: name=s4 [ 2.417321] regulator_enable_complete: name=s4 [ 2.430281] scsi host0: ufshcd [ 2.432717] regulator_enable: name=s7 [ 2.432851] regulator_enable_delay: name=s7 [ 2.435979] regulator_enable_complete: name=s7 [ 2.440039] regulator_enable: name=l1 [ 2.444533] regulator_enable: name=l2 [ 2.448330] regulator_enable_delay: name=l1 [ 2.451862] regulator_enable_complete: name=l1 [ 2.455948] regulator_enable_delay: name=l2 [ 2.460391] regulator_enable_complete: name=l2 [ 2.464483] clk_prepare: gcc_ufs_clkref_clk [ 2.468980] clk_prepare_complete: gcc_ufs_clkref_clk [ 2.473062] clk_prepare: gcc_ufs_phy_aux_clk [ 2.478266] clk_prepare_complete: gcc_ufs_phy_aux_clk [ 2.482529] clk_enable: gcc_ufs_clkref_clk [ 2.487464] clk_enable_complete: gcc_ufs_clkref_clk [ 2.491458] clk_enable: gcc_ufs_phy_aux_clk [ 2.496227] clk_enable_complete: gcc_ufs_phy_aux_clk [ 2.529237] ufshcd-qcom 1da4000.ufshc: ufshcd_print_pwr_info:[RX, TX]: gear=[1, 1], lane[1, 1], pwr[SLOWAUTO_MODE, SLOWAUTO_MODE], rate = 0 [ 2.529591] ufshcd_upiu: query_send: 1da4000.ufshc: HDR:00 00 00 1f 00 00 00 00 00 00 00 00, CDB:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 2.552289] ufshcd_command: send: 1da4000.ufshc: tag: 31, DB: 0x80000000, size: -1, IS: 0, LBA: 18446744073709551615, opcode: 0x0 [ 2.553914] ufshcd_command: dev_complete: 1da4000.ufshc: tag: 31, DB: 0x0, size: -1, IS: 0, LBA: 18446744073709551615, opcode: 0x0 [ 2.570111] clk: Not disabling unused clocks [ 2.577269] l9: supplied by bob [ 2.581452] ufshcd_wait_for_dev_cmd: max_timeout=500 jiffies=125 time_left=125 [ 2.584467] l10: supplied by bob [ 2.591633] ufshcd_upiu: query_complete: 1da4000.ufshc: HDR:00 00 00 1f 00 00 00 00 00 00 00 00, CDB:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 2.595096] ufshcd_upiu: query_send: 1da4000.ufshc: HDR:16 00 00 1f 00 81 00 00 00 00 00 00, CDB:06 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 2.608476] l13: supplied by bob [ 2.621199] ufshcd_command: send: 1da4000.ufshc: tag: 31, DB: 0x80000000, size: -1, IS: 0, LBA: 18446744073709551615, opcode: 0x0 [ 2.624533] l16: supplied by bob [ 2.636040] l18: supplied by bob [ 2.639317] l19: supplied by bob [ 2.642531] l21: supplied by bob [ 2.645743] l22: supplied by bob [ 2.649036] l23: supplied by bob [ 2.652160] l24: supplied by bob [ 2.655367] l25: supplied by bob [ 2.658589] l28: supplied by bob [ 2.663194] clk_set_rate: blsp2_uart2_apps_clk_src 3686400 [ 2.664999] clk_set_rate_complete: blsp2_uart2_apps_clk_src 3686400 [ 2.670260] clk_set_rate: gcc_blsp2_uart2_apps_clk 3686400 [ 2.676410] clk_set_rate_complete: gcc_blsp2_uart2_apps_clk 3686400 [ 5.856226] ufshcd_wait_for_dev_cmd: max_timeout=3000 jiffies=750 time_left=0 [ 5.856319] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: dev_cmd request timedout, tag 31 [ 5.862518] ufshcd_upiu: query_complete_err: 1da4000.ufshc: HDR:16 00 00 1f 00 81 00 00 00 00 00 00, CDB:06 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 5.871299] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11 [ 5.884894] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: failed with error -11, retries 0 [ 5.894359] ufshcd_upiu: query_send: 1da4000.ufshc: HDR:16 00 00 1f 00 81 00 00 00 00 00 00, CDB:06 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 5.903151] ufshcd_command: send: 1da4000.ufshc: tag: 31, DB: 0x80000000, size: -1, IS: 0, LBA: 18446744073709551615, opcode: 0x0 [ 5.968721] ufshcd-qcom 1da4000.ufshc: ufshcd_update_uic_error: UIC error flags = 0x00000000 [ 6.032370] ufshcd-qcom 1da4000.ufshc: ufshcd_update_uic_error: UIC error flags = 0x00000000 [ 6.102799] ufshcd-qcom 1da4000.ufshc: ufshcd_update_uic_error: UIC error flags = 0x00000001 [ 8.928202] ufshcd_wait_for_dev_cmd: max_timeout=3000 jiffies=750 time_left=0 [ 8.928269] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: dev_cmd request timedout, tag 31 [ 8.934392] ufshcd_upiu: query_complete_err: 1da4000.ufshc: HDR:16 00 00 1f 00 81 00 00 00 00 00 00, CDB:06 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 8.943267] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11 [ 8.956863] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: failed with error -11, retries 1 [ 8.966337] ufshcd_upiu: query_send: 1da4000.ufshc: HDR:16 00 00 1f 00 81 00 00 00 00 00 00, CDB:06 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 8.975125] ufshcd_command: send: 1da4000.ufshc: tag: 31, DB: 0x80000000, size: -1, IS: 0, LBA: 18446744073709551615, opcode: 0x0 [ 12.000193] ufshcd_wait_for_dev_cmd: max_timeout=3000 jiffies=750 time_left=0 [ 12.000261] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: dev_cmd request timedout, tag 31 [ 12.006386] ufshcd_upiu: query_complete_err: 1da4000.ufshc: HDR:16 00 00 1f 00 81 00 00 00 00 00 00, CDB:06 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 12.015259] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11 [ 12.028855] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: failed with error -11, retries 2 [ 12.038329] ufshcd_upiu: query_send: 1da4000.ufshc: HDR:16 00 00 1f 00 81 00 00 00 00 00 00, CDB:06 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 12.047114] ufshcd_command: send: 1da4000.ufshc: tag: 31, DB: 0x80000000, size: -1, IS: 0, LBA: 18446744073709551615, opcode: 0x0 [ 15.072195] ufshcd_wait_for_dev_cmd: max_timeout=3000 jiffies=750 time_left=0 [ 15.072262] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: dev_cmd request timedout, tag 31 [ 15.078385] ufshcd_upiu: query_complete_err: 1da4000.ufshc: HDR:16 00 00 1f 00 81 00 00 00 00 00 00, CDB:06 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 15.087259] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11 [ 15.100858] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: failed with error -11, retries 3 [ 15.110329] ufshcd_upiu: query_send: 1da4000.ufshc: HDR:16 00 00 1f 00 81 00 00 00 00 00 00, CDB:06 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 15.119115] ufshcd_command: send: 1da4000.ufshc: tag: 31, DB: 0x80000000, size: -1, IS: 0, LBA: 18446744073709551615, opcode: 0x0 [ 18.144193] ufshcd_wait_for_dev_cmd: max_timeout=3000 jiffies=750 time_left=0 [ 18.144261] ufshcd-qcom 1da4000.ufshc: ufshcd_wait_for_dev_cmd: dev_cmd request timedout, tag 31 [ 18.150387] ufshcd_upiu: query_complete_err: 1da4000.ufshc: HDR:16 00 00 1f 00 81 00 00 00 00 00 00, CDB:06 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 18.159256] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag: Sending flag query for idn 1 failed, err = -11 [ 18.172857] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: failed with error -11, retries 4 [ 18.182315] ufshcd-qcom 1da4000.ufshc: ufshcd_query_flag_retry: query attribute, opcode 6, idn 1, failed with error -11 after 5 retires [ 18.191105] ufshcd-qcom 1da4000.ufshc: ufshcd_complete_dev_init setting fDeviceInit flag failed with error -11 [ 18.203473] clk_disable: gcc_ufs_phy_aux_clk [ 18.213032] clk_disable_complete: gcc_ufs_phy_aux_clk [ 18.217461] clk_disable: gcc_ufs_clkref_clk [ 18.222385] clk_disable_complete: gcc_ufs_clkref_clk [ 18.226414] clk_unprepare: gcc_ufs_phy_aux_clk [ 18.231643] clk_unprepare_complete: gcc_ufs_phy_aux_clk [ 18.235858] clk_unprepare: gcc_ufs_clkref_clk [ 18.240969] clk_unprepare_complete: gcc_ufs_clkref_clk [ 18.245510] regulator_disable: name=l2 [ 18.250691] regulator_disable_complete: name=l2 [ 18.254253] regulator_disable: name=l1 [ 18.258751] regulator_disable_complete: name=l1 [ 18.262497] regulator_disable: name=s7 [ 18.266982] regulator_disable_complete: name=s7 [ 18.270748] regulator_disable: name=l20 [ 18.275268] regulator_disable_complete: name=l20 [ 18.278987] regulator_disable: name=bob [ 18.283913] regulator_disable_complete: name=bob [ 18.287447] regulator_disable: name=l26 [ 18.292346] regulator_disable_complete: name=l26 [ 18.295820] regulator_disable: name=s3 [ 18.300752] regulator_disable_complete: name=s3 [ 18.304250] regulator_disable: name=s4 [ 18.308741] regulator_disable_complete: name=s4 [ 18.312520] clk_disable: gcc_ufs_axi_clk [ 18.316911] clk_disable_complete: gcc_ufs_axi_clk [ 18.321086] clk_unprepare: gcc_ufs_axi_clk [ 18.325680] clk_unprepare_complete: gcc_ufs_axi_clk [ 18.329686] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk disabled [ 18.334482] clk_disable: gcc_aggre1_ufs_axi_clk [ 18.342439] clk_disable_complete: gcc_aggre1_ufs_axi_clk [ 18.346690] clk_disable: ufs_axi_clk_src [ 18.352236] clk_disable_complete: ufs_axi_clk_src [ 18.356155] clk_unprepare: gcc_aggre1_ufs_axi_clk [ 18.360755] clk_unprepare_complete: gcc_aggre1_ufs_axi_clk [ 18.365446] clk_unprepare: ufs_axi_clk_src [ 18.370817] clk_unprepare_complete: ufs_axi_clk_src [ 18.374906] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: bus_aggr_clk disabled [ 18.379705] clk_disable: gcc_ufs_ahb_clk [ 18.388006] clk_disable_complete: gcc_ufs_ahb_clk [ 18.391916] clk_unprepare: gcc_ufs_ahb_clk [ 18.396512] clk_unprepare_complete: gcc_ufs_ahb_clk [ 18.400513] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: iface_clk disabled [ 18.405314] clk_disable: gcc_ufs_unipro_core_clk [ 18.413268] clk_disable_complete: gcc_ufs_unipro_core_clk [ 18.417963] clk_disable: ufs_unipro_core_clk_src [ 18.423246] clk_disable_complete: ufs_unipro_core_clk_src [ 18.427949] clk_unprepare: gcc_ufs_unipro_core_clk [ 18.433236] clk_unprepare_complete: gcc_ufs_unipro_core_clk [ 18.437931] clk_unprepare: ufs_unipro_core_clk_src [ 18.443394] clk_unprepare_complete: ufs_unipro_core_clk_src [ 18.448262] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk_unipro disabled [ 18.453750] clk_disable: gcc_ufs_ice_core_clk [ 18.462052] clk_disable_complete: gcc_ufs_ice_core_clk [ 18.466575] clk_unprepare: gcc_ufs_ice_core_clk [ 18.471601] clk_unprepare_complete: gcc_ufs_ice_core_clk [ 18.476036] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: core_clk_ice disabled [ 18.481622] clk_disable: ln_bb_clk1 [ 18.489643] clk_disable_complete: ln_bb_clk1 [ 18.492871] clk_unprepare: ln_bb_clk1 [ 18.497522] clk_unprepare_complete: ln_bb_clk1 [ 18.500946] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: ref_clk disabled [ 18.505314] clk_disable: gcc_ufs_tx_symbol_0_clk [ 18.512834] clk_disable_complete: gcc_ufs_tx_symbol_0_clk [ 18.517704] clk_unprepare: gcc_ufs_tx_symbol_0_clk [ 18.522991] clk_unprepare_complete: gcc_ufs_tx_symbol_0_clk [ 18.527686] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: tx_lane0_sync_clk disabled [ 18.533185] clk_disable: gcc_ufs_rx_symbol_0_clk [ 18.541825] clk_disable_complete: gcc_ufs_rx_symbol_0_clk [ 18.546522] clk_unprepare: gcc_ufs_rx_symbol_0_clk [ 18.551811] clk_unprepare_complete: gcc_ufs_rx_symbol_0_clk [ 18.556506] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: rx_lane0_sync_clk disabled [ 18.562007] clk_disable: gcc_ufs_rx_symbol_1_clk [ 18.570649] clk_disable_complete: gcc_ufs_rx_symbol_1_clk [ 18.575344] clk_unprepare: gcc_ufs_rx_symbol_1_clk [ 18.580630] clk_unprepare_complete: gcc_ufs_rx_symbol_1_clk [ 18.585325] ufshcd-qcom 1da4000.ufshc: __ufshcd_setup_clocks: clk: rx_lane1_sync_clk disabled [ 18.590845] ufshcd_profile_clk_gating: 1da4000.ufshc: off: took 278316 usecs, err 0 [ 18.599520] ufshcd_init: 1da4000.ufshc: took 16087235 usecs, dev_state: UFS_ACTIVE_PWR_MODE, link_state: UIC_LINK_ACTIVE_STATE, err -11 [ 18.619047] Freeing unused kernel memory: 7232K
