On Tue, 5 Apr 2005, Russell King wrote: > > > physical bus: 31...24 23...16 15...8 7...0 > > > > > > BE version 1 (word invariant) > > > byte access byte 0 byte 1 byte 2 byte 3 > > > word access 31-24 23-16 15-8 7-0 > > > > > > BE version 2 (byte invariant) > > > byte access byte 3 byte 2 byte 1 byte 0 > > > word access 7-0 15-8 23-16 31-24 > > > > These are just representations of the same thing. However, I did > > deliberately elect not to try to solve this problem in the accessors. I > > know all about the register relayout, because 53c700 has to do that on > > parisc. > > They aren't. On some of our platforms, we have to exclusive-or the address > for byte accesses with 3 to convert to the right endian-ness. The same with certain MIPS configurations. And likewise you need to xor addresses with 2 for halfword accesses. > Sure, from the point of view of which byte each byte of a word represents, > it's true that they're indentical. But as far as the hardware is concerned, > they're definitely different. To clarify it a bit: both big and little endian representations are always the same -- it's going to a domain of the reverse endianness that can be done in two different ways, i.e. by preserving either bit or byte ordering (as described above). Depending on the interpretation of data being passed you want one or the other. That's why some systems provide ways of doing both kinds of accesses in hardware (e.g. the host bus to PCI bridge) to save CPU cycles needed for bit shuffling otherwise. Maciej - : send the line "unsubscribe linux-scsi" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
