On Tue, 2005-04-05 at 08:42 +0100, Russell King wrote: > Not so. There are two different styles of big endian. (Lets just face > it, BE is fucked in the head anyway...) > > physical bus: 31...24 23...16 15...8 7...0 > > BE version 1 (word invariant) > byte access byte 0 byte 1 byte 2 byte 3 > word access 31-24 23-16 15-8 7-0 > > BE version 2 (byte invariant) > byte access byte 3 byte 2 byte 1 byte 0 > word access 7-0 15-8 23-16 31-24 These are just representations of the same thing. However, I did deliberately elect not to try to solve this problem in the accessors. I know all about the register relayout, because 53c700 has to do that on parisc. However, I don't think it's the job of the io accessors to remap the register locations (primarily because the remapping depends on the documentation: a chip that's documented as BE on BE has no remapping required. Hoever, the same chip on LE would need this). > And guess which architecture implements *both* of these... Grumble. We have this in parisc too ... James - : send the line "unsubscribe linux-scsi" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
