On 15/02/2025 13:24, Ivaylo Ivanov wrote:
> The Exynos2200 SoC comes with 3 PHYs - snps eUSB2, snps USBDP combophy
> and a cut-off phy that origins from exynos5-usbdrd. The latter is used
> for link control, as well as pipe3 attachment and detachment.
>
> Add a new driver for it.
>
> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@xxxxxxxxx>
> ---
> drivers/phy/samsung/Kconfig | 13 ++
> drivers/phy/samsung/Makefile | 1 +
> drivers/phy/samsung/phy-exynos2200-usbcon.c | 241 ++++++++++++++++++++
> include/linux/soc/samsung/exynos-regs-pmu.h | 3 +
> 4 files changed, 258 insertions(+)
> create mode 100644 drivers/phy/samsung/phy-exynos2200-usbcon.c
>
> diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig
> index f62285254..47e9b9926 100644
> --- a/drivers/phy/samsung/Kconfig
> +++ b/drivers/phy/samsung/Kconfig
> @@ -90,6 +90,19 @@ config PHY_EXYNOS2200_SNPS_EUSB2
> This driver provides PHY interface for eUSB 2.0 controller
> present on Exynos5 SoC series.
>
> +config PHY_EXYNOS2200_USBCON
> + tristate "Exynos2200 USBCON PHY driver"
> + depends on (ARCH_EXYNOS && OF) || COMPILE_TEST
> + depends on HAS_IOMEM
> + depends on USB_DWC3_EXYNOS
How? What are you using from DWC3?
> + select GENERIC_PHY
> + select MFD_SYSCON
> + default y
> + help
> + Enable USBCON PHY support for Exynos2200 SoC.
> + This driver provides PHY interface for USB controller present
> + on Exynos2200 SoC.
> +
> config PHY_EXYNOS5_USBDRD
> tristate "Exynos5 SoC series USB DRD PHY driver"
> depends on (ARCH_EXYNOS && OF) || COMPILE_TEST
> diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile
> index 90b84c7fc..f70e12ddf 100644
> --- a/drivers/phy/samsung/Makefile
> +++ b/drivers/phy/samsung/Makefile
> @@ -15,5 +15,6 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o
> phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
> phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
> obj-$(CONFIG_PHY_EXYNOS2200_SNPS_EUSB2) += phy-exynos2200-snps-eusb2.o
> +obj-$(CONFIG_PHY_EXYNOS2200_USBCON) += phy-exynos2200-usbcon.o
> obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
> obj-$(CONFIG_PHY_EXYNOS5250_SATA) += phy-exynos5250-sata.o
> diff --git a/drivers/phy/samsung/phy-exynos2200-usbcon.c b/drivers/phy/samsung/phy-exynos2200-usbcon.c
> new file mode 100644
> index 000000000..7968c9792
> --- /dev/null
> +++ b/drivers/phy/samsung/phy-exynos2200-usbcon.c
> @@ -0,0 +1,241 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2025, Ivaylo Ivanov <ivo.ivanov.ivanov1@xxxxxxxxx>
> + */
> +
> +#include <linux/bitfield.h>
Are you using this header?
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/iopoll.h>
And rhis?
> +#include <linux/mfd/syscon.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/reset.h>
And this?
> +#include <linux/soc/samsung/exynos-regs-pmu.h>
> +
> +#define EXYNOS2200_USBCON_LINKCTRL 0x4
> +#define LINKCTRL_FORCE_QACT BIT(8)
> +
> +#define EXYNOS2200_USBCON_UTMI_CTRL 0x10
> +#define UTMI_CTRL_FORCE_VBUSVALID BIT(1)
> +#define UTMI_CTRL_FORCE_BVALID BIT(0)
> +
> +#define EXYNOS2200_USBCON_LINK_CLKRST 0xc
> +#define LINK_CLKRST_SW_RST BIT(0)
> +
> +struct exynos2200_usbcon_phy_drvdata {
> + const char * const *clk_names;
> + int n_clks;
> + const char * const *regulator_names;
> + int n_regulators;
> + u32 pmu_offset_usbcon_phy;
> +};
> +
> +struct exynos2200_usbcon_phy {
> + struct phy *phy;
> + void __iomem *base;
> + struct regmap *reg_pmu;
> + struct clk_bulk_data *clks;
> + const struct exynos2200_usbcon_phy_drvdata *drv_data;
> + u32 pmu_offset;
> + struct regulator_bulk_data *vregs;
> +};
> +
> +static void exynos2200_usbcon_phy_isol(struct exynos2200_usbcon_phy *inst,
> + bool isolate)
> +{
> + unsigned int val;
> +
> + if (!inst->reg_pmu)
> + return;
> +
> + val = isolate ? 0 : EXYNOS4_PHY_ENABLE;
> +
> + regmap_update_bits(inst->reg_pmu, inst->pmu_offset,
> + EXYNOS4_PHY_ENABLE, val);
> +}
> +
> +static void exynos2200_usbcon_phy_write_mask(void __iomem *base, u32 offset,
> + u32 mask, u32 val)
> +{
> + u32 reg;
> +
> + reg = readl_relaxed(base + offset);
> + reg &= ~mask;
> + reg |= val & mask;
> + writel_relaxed(reg, base + offset);
> +
> + /* Ensure above write is completed */
> + readl_relaxed(base + offset);
None of these should be relaxed.
> +}
> +
> +static int exynos2200_usbcon_phy_init(struct phy *p)
> +{
> + struct exynos2200_usbcon_phy *phy = phy_get_drvdata(p);
> + int ret;
> +
> + ret = regulator_bulk_enable(phy->drv_data->n_regulators, phy->vregs);
> + if (ret)
> + return ret;
> +
> + exynos2200_usbcon_phy_isol(phy, false);
> +
> + /*
> + * Disable HWACG (hardware auto clock gating control). This will force
> + * QACTIVE signal in Q-Channel interface to HIGH level, to make sure
> + * the PHY clock is not gated by the hardware.
> + */
> + exynos2200_usbcon_phy_write_mask(phy->base, EXYNOS2200_USBCON_LINKCTRL,
> + LINKCTRL_FORCE_QACT,
> + LINKCTRL_FORCE_QACT);
> +
> + /* Reset Link */
> + exynos2200_usbcon_phy_write_mask(phy->base,
> + EXYNOS2200_USBCON_LINK_CLKRST,
> + LINK_CLKRST_SW_RST,
> + LINK_CLKRST_SW_RST);
> +
> + fsleep(10); /* required after POR high */
> + exynos2200_usbcon_phy_write_mask(phy->base,
> + EXYNOS2200_USBCON_LINK_CLKRST,
> + LINK_CLKRST_SW_RST, 0);
> +
> + exynos2200_usbcon_phy_write_mask(phy->base,
> + EXYNOS2200_USBCON_UTMI_CTRL,
> + UTMI_CTRL_FORCE_BVALID |
> + UTMI_CTRL_FORCE_VBUSVALID,
> + UTMI_CTRL_FORCE_BVALID |
> + UTMI_CTRL_FORCE_VBUSVALID);
> +
> + return 0;
> +}
> +
> +static int exynos2200_usbcon_phy_exit(struct phy *p)
> +{
> + struct exynos2200_usbcon_phy *phy = phy_get_drvdata(p);
> +
> + exynos2200_usbcon_phy_isol(phy, true);
> +
> + regulator_bulk_disable(phy->drv_data->n_regulators, phy->vregs);
This looks like power off callback, not exit.
> +
> + return 0;
> +}
> +
> +static const struct phy_ops exynos2200_usbcon_phy_ops = {
> + .init = exynos2200_usbcon_phy_init,
> + .exit = exynos2200_usbcon_phy_exit,
> + .owner = THIS_MODULE,
> +};
> +
> +static int exynos2200_usbcon_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct exynos2200_usbcon_phy *phy;
> + const struct exynos2200_usbcon_phy_drvdata *drv_data;
> + struct phy_provider *phy_provider;
> + struct phy *generic_phy;
> + int ret;
> +
> + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
> + if (!phy)
> + return -ENOMEM;
> +
> + drv_data = of_device_get_match_data(dev);
> + if (!drv_data)
> + return -EINVAL;
> + phy->drv_data = drv_data;
> +
> + phy->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(phy->base))
> + return PTR_ERR(phy->base);
> +
> + phy->clks = devm_kcalloc(dev, drv_data->n_clks,
> + sizeof(*phy->clks), GFP_KERNEL);
> + if (!phy->clks)
> + return -ENOMEM;
> +
> + for (int i = 0; i < drv_data->n_clks; ++i)
> + phy->clks[i].id = drv_data->clk_names[i];
> +
> + ret = devm_clk_bulk_get(dev, phy->drv_data->n_clks,
> + phy->clks);
> + if (ret)
> + return dev_err_probe(dev, ret,
> + "failed to get phy clock(s)\n");
> +
> + phy->reg_pmu = syscon_regmap_lookup_by_phandle(dev->of_node,
> + "samsung,pmu-syscon");
syscon_regmap_lookup_by_phandle_args
> + if (IS_ERR(phy->reg_pmu)) {
> + dev_err(dev, "Failed to lookup PMU regmap\n");
> + return PTR_ERR(phy->reg_pmu);
> + }
> +
> + phy->pmu_offset = drv_data->pmu_offset_usbcon_phy;
> + phy->vregs = devm_kcalloc(dev, drv_data->n_regulators,
> + sizeof(*phy->vregs), GFP_KERNEL);
> + if (!phy->vregs)
> + return -ENOMEM;
> + regulator_bulk_set_supply_names(phy->vregs,
> + drv_data->regulator_names,
> + drv_data->n_regulators);
> + ret = devm_regulator_bulk_get(dev, drv_data->n_regulators,
> + phy->vregs);
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to get regulators\n");
> +
> + generic_phy = devm_phy_create(dev, NULL, &exynos2200_usbcon_phy_ops);
> + if (IS_ERR(generic_phy)) {
> + dev_err(dev, "failed to create phy %d\n", ret);
> + return PTR_ERR(generic_phy);
> + }
> +
> + dev_set_drvdata(dev, phy);
> + phy_set_drvdata(generic_phy, phy);
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (IS_ERR(phy_provider)) {
> + dev_err(dev, "failed to register phy provider\n");
> + return PTR_ERR(phy_provider);
Same comments as on previous patch.
Best regards,
Krzysztof
