Exynos990 uses the same version of USI SPI (v2.1) as the GS101. Removed fifo_lvl_mask and rx_lvl_offset, and changed to the new data configuration port. The difference from other new port configuration data is that fifo_depth is only specified in fifo-depth in DT. Exynos 990 data for SPI: - The depth of the FIFO is not the same size on all nodes. A depth of 64 bytes is used on most nodes, while a depth of 256 bytes is used on 3 specific nodes (SPI 8/9/10). - The Exynos 990 only allows access to 32-bit registers. If access is attempted with a different size, an error interrupt is generated. Therefore, it is necessary to perform write accesses to registers in 32-bit blocks. Changes in v2: - Added a default "fifo_depth = 64" to prevent crashes when "fifo-depth" is missing in the device tree (avoids divide-by-zero issues). - No other functional changes. Changes in v3: - Reordered fifo_depth handling in s3c64xx_spi_probe() so that the DT property takes precedence over the default value in port_config. This allows node-specific FIFO depths to be applied correctly while preserving a fallback. Denzeel Oliva (3): spi: dt-bindings: samsung: add samsung,exynos990-spi compatible spi: s3c64xx: prioritize fifo-depth from DT over port_config spi: s3c64xx: add support exynos990-spi to new port config data .../devicetree/bindings/spi/samsung,spi.yaml | 1 + drivers/spi/spi-s3c64xx.c | 29 +++++++++++++++---- 2 files changed, 25 insertions(+), 5 deletions(-) -- 2.48.1
