Hi André,
On Wed, 27 Nov 2024 at 10:58, André Draszik <andre.draszik@xxxxxxxxxx> wrote:
>
> USB SS lanes need to be configured based the connector orientation -
small nit: "based the" -> "based on the"
> at most two lanes will be in use for USB (and the remaining two for
> alternate modes like DP).
>
> For the USB link to come up in SS, the lane configuration registers
> have to be programmed accordingly.
>
> While we still need a way to be notified of the actual connector
> orientation and then reprogram the registers accordingly (at the moment
> the configuration happens just once during phy_init() and never again),
> we can prepare the code doing the configuration to take the orientation
> into account.
>
> Do so.
>
> Note: the mutex is needed to synchronize this with the upcoming
> connector orientation callback.
>
> Signed-off-by: André Draszik <andre.draszik@xxxxxxxxxx>
> ---
> drivers/phy/samsung/phy-exynos5-usbdrd.c | 72 ++++++++++++++++++++++----------
> 1 file changed, 51 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> index c1ce6fdeef31..1a34e9b4618a 100644
> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> @@ -23,6 +23,7 @@
> #include <linux/regmap.h>
> #include <linux/regulator/consumer.h>
> #include <linux/soc/samsung/exynos-regs-pmu.h>
> +#include <linux/usb/typec_mux.h>
>
> /* Exynos USB PHY registers */
> #define EXYNOS5_FSEL_9MHZ6 0x0
> @@ -209,6 +210,10 @@
>
> #define EXYNOS9_PMA_USBDP_CMN_REG00B8 0x02e0
> #define CMN_REG00B8_LANE_MUX_SEL_DP GENMASK(3, 0)
> +#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE3 BIT(3)
> +#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE2 BIT(2)
> +#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE1 BIT(1)
> +#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE0 BIT(0)
>
> #define EXYNOS9_PMA_USBDP_CMN_REG01C0 0x0700
> #define CMN_REG01C0_ANA_LCPLL_LOCK_DONE BIT(7)
> @@ -383,11 +388,13 @@ struct exynos5_usbdrd_phy_drvdata {
> * @clks: clocks for register access
> * @core_clks: core clocks for phy (ref, pipe3, utmi+, ITP, etc. as required)
> * @drv_data: pointer to SoC level driver data structure
> + * @phy_mutex: mutex protecting phy_init/exit & TCPC callbacks
> * @phys: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
> * instances each with its 'phy' and 'phy_cfg'.
> * @extrefclk: frequency select settings when using 'separate
> * reference clocks' for SS and HS operations
> * @regulators: regulators for phy
> + * @orientation: TypeC connector orientation - normal or flipped
> */
> struct exynos5_usbdrd_phy {
> struct device *dev;
> @@ -397,6 +404,7 @@ struct exynos5_usbdrd_phy {
> struct clk_bulk_data *clks;
> struct clk_bulk_data *core_clks;
> const struct exynos5_usbdrd_phy_drvdata *drv_data;
> + struct mutex phy_mutex;
> struct phy_usb_instance {
> struct phy *phy;
> u32 index;
> @@ -406,6 +414,8 @@ struct exynos5_usbdrd_phy {
> } phys[EXYNOS5_DRDPHYS_NUM];
> u32 extrefclk;
> struct regulator_bulk_data *regulators;
> +
> + enum typec_orientation orientation;
typec_orientation is defined in #include <linux/usb/typec.h> so it
should be added to the includes
Apart from that
Reviewed-by: Peter Griffin <peter.griffin@xxxxxxxxxx>
Tested-by: Peter Griffin <peter.griffin@xxxxxxxxxx>
Validated that a super-speed USB link is established between Pixel 6
phone and my laptop with this patch applied and that adb works.
regards,
Peter
