On 04/08/2024 23:53, David Virag wrote:
> The Exynos7885 SoC has an Exynos USB PHY that theoretically supports
> USB3 SuperSpeed, but all known devices using it only have USB2 and the
> vendor driver has USB3 function stubbed out, so we'll only support USB2.
>
> Apart from this mysterius USB3 capability, it's the closest to Exynos850
> out of those supported. Unlike other SoCs though, this one doesn't set
> the reference clock by default, so we have to set it manually.
> For this, create a set_ref_clk_rate property in drvdata that can be set
> to a predefined value to set the clockrate to.
>
> Signed-off-by: David Virag <virag.david003@xxxxxxxxx>
> ---
> drivers/phy/samsung/phy-exynos5-usbdrd.c | 21 +++++++++++++++++++++
> include/linux/soc/samsung/exynos-regs-pmu.h | 3 +++
> 2 files changed, 24 insertions(+)
>
> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> index df52b78a120b..466c72d8a93c 100644
> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
> @@ -367,6 +367,7 @@ struct exynos5_usbdrd_phy_drvdata {
> int n_clks;
> const char * const *core_clk_names;
> int n_core_clks;
> + u32 set_ref_clk_rate;
Rate is in unsigned long.
Best regards,
Krzysztof
